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    • 51. 发明专利
    • DIGITAL DIFFERENTIAL ANALYZING MACHINE
    • JPS5987544A
    • 1984-05-21
    • JP19750882
    • 1982-11-12
    • HITACHI LTD
    • KODAMA KAZUYUKIYABUUCHI SHIGERUENDOU TAKESHITOMITA NOBUO
    • G06F7/64
    • PURPOSE:To obtain a digital differential analyzing machine of an arithmetic system for floating point, which is applicable to a small-sized dynamic simulator at a high speed, by using an element corresponding to LSTTL so that an integral calculation within 1mu sec can be executed. CONSTITUTION:N sets of basic arithmetic units ALU 1a, 1b-6 of the same constitution, which are connected in accordance with a prescribed data flow are provided on an adding and subtracting circuit for floating point of a digital differential analyzing machine DDA. A partial calculation of a DDA operator of the M-th stage, another partial calculation of a DDA operator of the following (M+1)-th stage, and a partial operation of a DDA operator of the preceding M-1-th stage are executed in parallel by said ALUs 1a, 1b-6, an ALU of the pre-stage by one, and an ALU of the post-stage by one, respectively. With respect to said each ALU 1a, 1b-6, a controlling circuit by N pieces of control information transfer registers OT1-OT7, XT1-XT7, AT1-AT7 and Y1B- Y4B, and programmable logic arrays ALA4-7 is provided. In this state, the integral calculation within 1mu sec is executed by using an element corresponding to LSTTL.