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    • 54. 发明专利
    • SIGNAL TRANSMITTING DEVICE
    • JPS56112160A
    • 1981-09-04
    • JP1531480
    • 1980-02-08
    • HITACHI LTD
    • MIZOKAWA SADAOOKADA MASAKAZU
    • H04L5/14H04L12/437H04L29/14
    • PURPOSE:To enable easy diagnosis of a device by sending prescribed data from transmitting side of the device section and checking normality of the transmitting device by comparing said data with the transmission data after receiving this with the same transmitting device. CONSTITUTION:Data sent from other transmitting device through transmission path 50 are received and transferred to a device section 61 connected to the transmitting device. In the case where the data are sent to other device section 61, the transmission data sent from the device section are inputted to a control section 71, and the data are sent to other transmission path through a transmission path 51 via a transmitting and receiving section 81, a switching section 91. In testing mode, trnamitting and receiving terminals of the transmitting device are connected and a self loop is formed independently by the transmitting device to be tested. Prescribed data are sent from the transmitting side of the device section 61. After receiving the data by the same transmitting device, normality of the transmission data. Thus, the device is diagnosed easily.
    • 57. 发明专利
    • ADDRESS CONTROL CIRCUIT
    • JPS5559549A
    • 1980-05-06
    • JP13149878
    • 1978-10-27
    • HITACHI LTD
    • MIZOKAWA SADAO
    • G06F9/26G06F9/22
    • PURPOSE:To obtain a high-speed address control circuit featuring the low power consumption by providing the gate circuit which generates the signal to control the flow of the microprogram plus the flip-flop which detects the satisfaction of the conditions at execution of the conditional branch order. CONSTITUTION:FF28-32 are reset for the period when flag FF7-11 are not set and while the unsatisfaction of the conditions is detected at detector circuits 17-21 for registers 12-16. At the same time, the conditions of gate 33 output is not satisfied, and FF35 which shifted the output is reset. And the state of control signal 6X is varied for gate 36 when the output of gate 33 arrives. After setting the conditional flag, the output of gate 33 is delivered, and the output of 6X of gate 36 is delivered. The output of gate 33 is shifted in the next cycle to shift the output of FF34 memorised to FF35, and the output of gate 33 is extracted at gate 36 to inhibit signal 6X. At the same time, the output of FF34 resets FF7-11 via gate 22.