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51. 发明专利

JP2007258751A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007258751A
公开(公告)日：2007-10-04
申请号：JP2007166097
申请日：2007-06-25
申请人： Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人： ISHIMURA DAIKI , TAKAHASHI KATSUNORI , SAKAMOTO MITSURU , ASARI TADASHI
IPC分类号： H01L25/065 , H01L21/60 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/45 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/48257 , H01L2224/49 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve the performance of a lamination-type semiconductor device for satisfying a decrease in packaging height, that in a packaging area, and that in weight, and to reduce costs in an existing manufacturing line. SOLUTION: The semiconductor device made of an insulating resin, where a tab is formed in a frame shape, includes: a sealant 4 made of an insulating resin; a tab 1e for supporting a semiconductor chip; a plurality of leads 1a for exposing one surface to the packaging surface of the sealant; a first semiconductor chip 2 that is positioned in the sealing body, has a first main surface that is a circuit formation surface and a first back at a side opposite to the first main surface, and is supported on one surface of the tab; a plurality of first electrode pads 2a formed on the first main surface of the first semiconductor chip; a second semiconductor chip 3 that has a wire 5 for electrically connecting the electrode pad to the lead, a second main surface that is a circuit formation surface, and a second back at a side opposite to the second main surface, and is mounted in a stack on the first main surface of the first semiconductor chip; and the wire 5 for electrically connecting the plurality of first electrode pads of the first semiconductor chip to the lead, and a plurality of second electrode pads formed on the second main surface of the second semiconductor chip to the lead. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提高层压型半导体器件的性能，以满足包装高度的降低，包装面积和重量的降低，并降低现有生产线中的成本。解决方案：由绝缘树脂制成的半导体器件，其中突片形成为框架形状，包括：由绝缘树脂制成的密封剂4; 用于支撑半导体芯片的突片1e; 用于将一个表面暴露于密封剂的包装表面的多个引线1a; 位于密封体中的第一半导体芯片2具有作为电路形成面的第一主表面和与第一主表面相对的一侧的第一背面，并被支撑在凸片的一个表面上; 形成在第一半导体芯片的第一主表面上的多个第一电极焊盘2a; 第二半导体芯片3，其具有用于将电极焊盘电连接到引线的导线5，作为电路形成表面的第二主表面和与第二主表面相对的一侧的第二背面，并且安装在堆叠在第一半导体芯片的第一主表面上; 以及用于将第一半导体芯片的多个第一电极焊盘电连接到引线的导线5以及形成在第二半导体芯片的第二主表面上的多个第二电极焊盘。版权所有（C）2008，JPO＆INPIT

52. 发明专利

JP3943145B2 Resin sealing method of the mold of the cleaning method and a semiconductor chip 失效
公开(公告)号：JP3943145B2
公开(公告)日：2007-07-11
申请号：JP27093894
申请日：1994-11-04
申请人：株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人：清土田
IPC分类号： B29C33/72 , B29C45/02 , H01L21/56
CPC分类号： B29C33/72

53. 发明专利

JP2007081425A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007081425A
公开(公告)日：2007-03-29
申请号：JP2006317988
申请日：2006-11-27
申请人： Hitachi Ltd , Renasas Northern Japan Semiconductor Inc , 株式会社ルネサス北日本セミコンダクタ , 株式会社日立製作所
发明人： FUJISAWA ATSUSHI , KONNO TAKASHI , OSAKA SHINGO , HARUTA AKIRA , ICHITANI MASAHIRO
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H01L24/32 , H01L24/73 , H01L2224/32057 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/83385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of deformation such as warp and distortion of a base substrate, when an insulating layer is disposed over the whole region on the base substrate made of a flexible film. SOLUTION: In the semiconductor device, wiring conductors (electrode pads 2 for bump connection, wiring 3, electrode pads 4 for wire connection, and wiring 5 for plating) is arranged on one surface of the base substrate 1 made of the flexible film, and a semiconductor chip 10 is mounted on the surface of the flexible film through an adhesive 12, wherein the insulating layer 9 is divided into a plurality of portions to locate them on each wiring conductor. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了防止基底基板的翘曲和变形等变形的发生，当在由柔性膜制成的基底基板上的整个区域上设置绝缘层时。解决方案：在半导体器件中，布线导体（用于凸块连接的电极焊盘2，用于焊接连接的电极焊盘2，用于电线连接的电极焊盘4和用于电镀的布线5）布置在由柔性材料制成的基底基板1的一个表面上膜和半导体芯片10通过粘合剂12安装在柔性膜的表面上，其中绝缘层9被分成多个部分以将它们定位在每个布线导体上。版权所有（C）2007，JPO＆INPIT

54. 发明专利

JP3844120B2 Semiconductor device 有权
公开(公告)号：JP3844120B2
公开(公告)日：2006-11-08
申请号：JP2001321298
申请日：2001-10-19
申请人：株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人：寛嗣中村
IPC分类号： G06F3/00 , H03K19/0175 , G11C7/10
CPC分类号： G11C7/1006 , G11C2216/30

55. 发明专利

JP3839323B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP3839323B2
公开(公告)日：2006-11-01
申请号：JP2002012775
申请日：2002-01-22
申请人：株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人：滋中村 , 正克後藤
IPC分类号： H01L25/18 , H01L21/60 , H01L23/31 , H01L25/065 , H01L25/07
CPC分类号： H01L24/49 , H01L23/3128 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/1134 , H01L2224/131 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/49171 , H01L2224/4945 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2224/85191 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2225/06568 , H01L2225/06575 , H01L2225/06582 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2924/00011 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor device having a stack structure comprises: a single-piece substrate having a chip support surface serving as a main surface, a back surface, a plurality of connection terminals provided on the chip support surface and a plurality of solder balls provided on the back surface; a first semiconductor chip having a main surface, aback surface, a plurality of semiconductor devices on the main surface of the first semiconductor chip and a plurality of pads provided on the main surface of the first semiconductor chip; a second semiconductor chip having a main surface, a back surface, a plurality of semiconductor devices provided on the main surface of the second semiconductor chip and a plurality of pads provided on the main surface of the second semiconductor chip; and a resin sealing body formed on the chip support surface of the single-piece substrate and used for sealing the first semiconductor chip and the second semiconductor chip; and a plurality of wires for connecting the pads of the second semiconductor chip to the respective connection terminals provided on the single-piece substrate. In the stack structure, the second semiconductor chip is made thinner than the first semiconductor chip. As a result, the structure package of the semiconductor device can be made thin.

56. 发明专利

JP3839321B2 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：JP3839321B2
公开(公告)日：2006-11-01
申请号：JP2001508498
申请日：2000-06-30
申请人：株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人：好彦嶋貫
IPC分类号： H01L23/50 , H01L21/56 , H01L23/31 , H01L23/495
CPC分类号： H01L23/49503 , H01L21/4825 , H01L21/4842 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/49513 , H01L23/4952 , H01L23/49541 , H01L23/49548 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/743 , H01L24/78 , H01L24/83 , H01L24/85 , H01L2224/05554 , H01L2224/29 , H01L2224/29007 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/29298 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/73265 , H01L2224/743 , H01L2224/78301 , H01L2224/83192 , H01L2224/8385 , H01L2224/85181 , H01L2224/85205 , H01L2224/92 , H01L2224/92247 , H01L2224/97 , H01L2924/00013 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/0103 , H01L2924/0105 , H01L2924/01047 , H01L2924/01082 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2924/00012
摘要： A semiconductor device is disclosed which includes a tab (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tab suspension lead (4) for support of the tab (5), a plurality of electrical leads (2) which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section (12) and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove (2e) and outer groove (2f) in a wire bonding surface (2d) as disposed within the seal section (12) of said to-be-connected portion, and wires (10) for electrical connection between the leads (2) and pads (7) of the semiconductor chip (8), wherein said thickness reduced portion of the leads (2) is covered by or coated with a sealing resin material while causing the wires (10) to be contacted with said to-be-connected portion at specified part lying midway between the outer groove (2f) and inner groove (2e) to thereby permit said thickness reduced portion of leads (2) and the outer groove (2f) plus the inner groove (2e) to prevent occurrence of any accidental lead drop-down detachment.

57. 发明专利

JP3827520B2 Semiconductor device 有权
公开(公告)号：JP3827520B2
公开(公告)日：2006-09-27
申请号：JP2000335839
申请日：2000-11-02
申请人：株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人：貴史今野 , 亮一太田 , 次彦平野 , 敦藤沢
IPC分类号： H01L21/52 , H01L23/12 , H01L21/301 , H01L21/56 , H01L21/58 , H01L21/68 , H01L23/00 , H01L23/14 , H01L23/16 , H01L23/28 , H01L23/31 , H01L23/498
CPC分类号： H01L21/6836 , H01L21/565 , H01L23/16 , H01L23/3128 , H01L23/49816 , H01L23/564 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2221/68327 , H01L2224/274 , H01L2224/2919 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/73265 , H01L2224/83191 , H01L2224/8385 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is disclosed, comprising a tape substrate which supports a semiconductor chip, an insulating adhesive layer disposed between the semiconductor chip and the tape substrate, an insulating sheet member laminated to the insulating adhesive layer and formed harder than the insulating adhesive layer, wires for connecting pads on the semiconductor chip with connecting terminals on the tape substrate, a sealing portion formed by sealing the semiconductor chip with resin, and plural solder balls provided on a back of the tape substrate. A die bonding layer for fixing the semiconductor chip thereto is composed of an insulating adhesive layer and the insulating sheet member laminated thereto. The die bonding layer is formed thick by such a multi-layer structure, whereby the resin balance of the surface and back of the semiconductor chip is improved to prevent warping of a package and improve the mounting temperature cyclicity and reflow characteristic.

58. 发明专利

JP2006236022A Image processor 审中-公开
标题翻译：图像处理器
公开(公告)号：JP2006236022A
公开(公告)日：2006-09-07
申请号：JP2005050021
申请日：2005-02-25
申请人： Renasas Northern Japan Semiconductor Inc , 株式会社ルネサス北日本セミコンダクタ
发明人： TAKANO HIROYUKI , UCHIYAMA YOSHIHARU , SHIRAI SEIICHI
IPC分类号： G06T1/00 , B60R1/00 , G01B11/00 , G01C3/06 , H04N7/18 , H04N13/00
摘要： PROBLEM TO BE SOLVED: To provide an image processor for performing disparity calculation processing at a high speed.
SOLUTION: The image processor includes a disparity calculating part for performing the parallax calculation processing, based on first and second images; and first and second buffers for respectively able to hold a work image which is used for the disparity calculation processing. The parallax calculation processing includes first processing of acquiring a first difference image, by subtracting between the first and second images (S12); second processing of adding and averaging the pixel values of the first difference images (S13); third processing of comparing the added and averaged image with the work image in the first buffer, so as to update the pixel value of the work image in the first buffer through the use of a small value (S14); fourth processing of acquiring a second difference image, by subtracting between the work image in the first buffer and the work image in the second buffer (S15); and fifth processing of converting the pixel value of the second difference image (S16). Consequently, the disparity calculation processing is fully performed with a CPU having general throughput.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于高速执行视差计算处理的图像处理器。解决方案：图像处理器包括基于第一和第二图像执行视差计算处理的视差计算部分; 以及用于分别能够保持用于视差计算处理的工作图像的第一和第二缓冲器。视差计算处理包括通过在第一和第二图像之间减去来获取第一差分图像的第一处理（S12）; 对第一差分图像的像素值进行加法和平均的第二处理（S13）; 将加法和平均图像与第一缓冲器中的工作图像进行比较的第三处理，以便通过使用小值来更新第一缓冲器中的工作图像的像素值（S14）; 通过在第一缓冲器中的工作图像与第二缓冲器中的工作图像之间减去来获得第二差分图像的第四处理（S15）; 以及转换第二差分图像的像素值的第五处理（S16）。因此，具有一般吞吐量的CPU完全执行视差计算处理。版权所有（C）2006，JPO＆NCIPI

59. 发明专利

JP2006231926A Manufacturing process of semiconductor device 审中-公开
标题翻译：半导体器件的制造工艺
公开(公告)号：JP2006231926A
公开(公告)日：2006-09-07
申请号：JP2006105775
申请日：2006-04-07
申请人： Renasas Northern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人： TSUCHIDA KIYOSHI
IPC分类号： B29C33/72 , B29C45/14 , B29L31/34 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing process of a molding-die-cleanable semiconductor device, which allows efficient elimination of smudges in the molding die.
SOLUTION: A molding die cleaning sheet 8, to which a large number of pores capable of passing particles of a cleaning resin 9 are formed allover, is prepared. The molding die cleaning sheet 8 is clamped so that it contacts throughout mating face of a molding die 1 comprising an upper die 1a and a lower die 1b. The cleaning resin 9 is pressurized and filled in the molding die 1 while infiltrating the molding die cleaning sheet 8. After a certain period of time, the first die 1a and the second die 1b are separated, and the molding die cleaning sheet 8, with the cleaning resin 9 adhered, is taken out.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可模制可清洗半导体器件的制造工艺，其能够有效地消除成型模具中的污迹。＆lt; P＆gt;解决方案：准备形成能够通过清洁树脂9的颗粒的大量孔的成形模清洁片8。成型模具清洁片8被夹紧，使得其与包括上模1a和下模1b的成型模具1的配合面接触。在将成型模具清洁片8浸渍的同时，将清洗树脂9加压填充到成型模具1中。经过一定时间后，将第一模具1a和第二模具1b分离，成型模具清洁薄片8与取出附着的清洁树脂9。版权所有（C）2006，JPO＆NCIPI

60. 发明专利

JP3813797B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP3813797B2
公开(公告)日：2006-08-23
申请号：JP2000207495
申请日：2000-07-07
申请人：株式会社ルネサステクノロジ , 株式会社ルネサス北日本セミコンダクタ
发明人：義之 ▲角▼ , 育生吉田 , 月夫船木 , 広菊地
IPC分类号： H01L21/60 , H01L25/18 , H01L23/498 , H01L23/528 , H01L25/04 , H01L27/14
CPC分类号： H01L24/81 , H01L23/49838 , H01L23/528 , H01L2224/1134 , H01L2224/13144 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2924/351 , H01L2924/00
摘要： Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.

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