专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JP2003007840A Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2003007840A
公开(公告)日：2003-01-10
申请号：JP2001190652
申请日：2001-06-25
申请人： Nec Corp , 日本電気株式会社
发明人： TANOMURA MASAHIRO , SHIMAWAKI HIDENORI , NIWA SHIGEKI , AZUMA KOJI , KUROSAWA NAOTO
IPC分类号： H01L21/331 , H01L21/329 , H01L21/8222 , H01L21/8252 , H01L27/06 , H01L29/737 , H01L29/868
CPC分类号： H01L27/0605 , H01L21/8252 , H01L29/7371 , H01L29/868
摘要： PROBLEM TO BE SOLVED: To form an HBT and a PIN diode simultaneously on a same semiconductor substrate and to achieve low cost without deteriorating reliability of the HBT. SOLUTION: A method of manufacturing a semiconductor device is implemented, which comprises a step of forming an emitter electrode 108 on a fifth layer of a substrate 101 having epitaxial film, where a first layer to the fifth layer are laminated on a surface, a step of etching the fifth layer to form emitter cap layers (106, 107), a step of forming a base electrode 109 and a P-layer electrode 119 by metal diffusion to the top portions of a fourth layer to a third layer, a step of etching from the fourth layer to a second layer to form an emitter layer 105, a base layer 104, a collector layer 103, an N-type semiconductor layer 115, a P-layer 114 and an I-layer 113, a step of forming an element isolation film region 111 on the first layer to form a sub-collector layer 102 and an N-layer 112, and a step of forming a collector electrode 110 and an N-layer electrode 120 on the sub-collector 102.
摘要翻译：要解决的问题：在相同的半导体衬底上同时形成HBT和PIN二极管并且实现低成本而不降低HBT的可靠性。解决方案：实现一种制造半导体器件的方法，其包括在具有外延膜的基板101的第五层上形成发射电极108的步骤，其中第一层至第五层层压在表面上，步骤蚀刻第五层以形成发射极帽层（106,107），通过金属扩散形成基极109和P层电极119到第四层至第三层的顶部的步骤;步骤从第四层蚀刻到第二层以形成发射极层105，基极层104，集电极层103，N型半导体层115，P层114和I层113，形成步骤在第一层上形成元件隔离膜区域111，以形成副集电极层102和N层112;以及在子集电极102上形成集电极110和N层电极120的步骤。

42. 发明专利

JP2003007706A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2003007706A
公开(公告)日：2003-01-10
申请号：JP2001194078
申请日：2001-06-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , SHIODA TAKASHI
IPC分类号： G03F7/038 , G03F7/40 , H01L21/28 , H01L21/288 , H01L21/308 , H01L21/3205 , H01L21/331 , H01L21/335 , H01L21/768 , H01L21/8252 , H01L23/52 , H01L27/06 , H01L27/095 , H01L29/737
CPC分类号： H01L29/66318 , H01L21/3081 , H01L21/76898 , H01L21/8252 , H01L27/0605 , H01L29/66462
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device for using a mask material that has excellent dry etching resistance and can be formed at low temperature to achieve a fine via hole and a high yield in a semiconductor via hole-machining process, and achieving a high-performance ultra-high-frequency semiconductor device. SOLUTION: A light-sensitive polyimide resin is used as a mask for etching machining. In the light-sensitive polyimide, a mask process due to a projection aligner can be made as in resist, and film thickness formation of 10 to 40 μm can also be made easily. Etching resistance is excellent, and by vitrifying it through curing treatment at a relatively low temperature of 200 to 250 deg.C, the selectivity ratio can be improved up to approximately 20.
摘要翻译：要解决的问题：为了提供使用具有优异的耐干蚀刻性的掩模材料的半导体器件的制造方法，并且可以在低温下形成以在半导体通孔加工过程中实现细通孔和高产率，并实现了高性能超高频半导体器件。解决方案：使用光敏聚酰亚胺树脂作为蚀刻加工的掩模。在光敏聚酰亚胺中，可以制成由于投影对准器而形成的掩模工艺，如抗蚀剂，并且也可以容易地形成10μm至40μm的膜厚度。耐蚀性优异，通过在200〜250℃的较低温度下进行固化处理使其玻璃化，可以使选择比提高至20左右。

43. 发明专利

JP2002319589A SEMICONDUCTOR DEVICE AND POWER AMPLIFIER COMPRISING IT 失效
公开(公告)号：JP2002319589A
公开(公告)日：2002-10-31
申请号：JP2001121973
申请日：2001-04-20
申请人： HITACHI LTD
发明人： MOCHIZUKI KAZUHIRO , OKA TORU , OBE ISAO , YAMASHITA KIICHI
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8252 , H01L27/06 , H01L29/737 , H03F1/30
摘要： PROBLEM TO BE SOLVED: To realize a highly reliable power amplifier operable or a power supply voltage not higher than 2V with high power conversion efficiency at a low cost. SOLUTION: The semiconductor device comprises a plurality of heterojunction bipolar transistors each having a base layer of GaAsSb or InGaAs, a GaAs substrate, and a buffer layer interposed between the base layer and the substrate wherein the substrate and the buffer layer directly under the intrinsic region of the plurality of heterojunction bipolar transistors are eliminated partially or entirely. A power amplifier having high power conversion efficiency can thereby be realized.

44. 发明专利

JP2002124523A GaAs SEMICONDUCTOR POWER SUPPLY DEVICE OPERABLE WITH LOW-VOLTAGE POWER SUPPLY AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002124523A
公开(公告)日：2002-04-26
申请号：JP2001306688
申请日：2001-10-02
申请人： KOREA ELECTRONICS TELECOMM
发明人： LEE JONG-LAM , KIM HAE-CHEON , MUN JAE-KYOUNG , PARK HYUNG-MOO
IPC分类号： H01L29/812 , H01L21/338 , H01L21/76 , H01L21/8252 , H01L29/10 , H01L29/45
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device by which the influx of the parasitic carrier at the interface between a substrate and a buffer layer to a channel layer can be prevented, and to provide a method for manufacturing the semiconductor device. SOLUTION: A first GaAs buffer layer 10A which is not doped is formed on a semi-insulating GaAs substrate 70, and a superlattice layer 80 is formed on the first GaAs buffer layer 10A. A second GaAs buffer layer 10B which is of the identical material with the first GaAs buffer layer 10A and is not doped is formed on the superlattice layer 80. A channel layer 20 is formed on the second GaAs buffer layer 10B, and a surface protecting film 30 is formed on the channel layer 20.

45. 发明专利

JP2001511948A 失效
公开(公告)号：JP2001511948A
公开(公告)日：2001-08-14
申请号：JP53424998
申请日：1998-02-06
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8252 , H01L27/06 , H01L29/205 , H01S5/026 , H01S5/343
摘要： A heterobipolar transistor HBT and a laser diode LD are manufactured from a common epitaxial structure having a plurality of semiconducting layers. The transistor can be manufactured directly from the material as it is after finishing the epitaxial steps. For manufacturing the laser diode the structure is changed by diffusing zinc into the material, so that the topmost material layers change their dopant type from n-type to p-type. This is made on selected areas of a wafer, so that transistors and laser diodes thereby can be monolithically integrated. The active region of the laser is located in the collector of the transistor, which gives a freedom in designing the components and results in that an individual optimization of the two components can be made. The laser and the HBT can thus be given substantially the same structures, as if they had been individually optimized. The laser will for example be the type vertical injection and can therefor get the same performance as discrete lasers.

46. 发明专利

JP3101457B2 失效
公开(公告)号：JP3101457B2
公开(公告)日：2000-10-23
申请号：JP240793
申请日：1993-01-11
IPC分类号： H01L21/306 , H01L21/331 , H01L21/335 , H01L21/336 , H01L21/337 , H01L21/338 , H01L21/8252 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/778 , H01L29/78 , H01L29/812

47. 发明专利

JP2891204B2 失效
公开(公告)号：JP2891204B2
公开(公告)日：1999-05-17
申请号：JP25642496
申请日：1996-09-27
申请人： NIPPON DENKI KK
发明人： OIKAWA YOICHI
IPC分类号： H01L21/338 , H01L21/8232 , H01L21/8252 , H01L27/06 , H01L27/095 , H01L29/778 , H01L29/812 , H01L21/06

48. 发明专利

JP2580451B2 失效
公开(公告)号：JP2580451B2
公开(公告)日：1997-02-12
申请号：JP31476492
申请日：1992-11-25
申请人： KANKOKU DENSHI TSUSHIN KENKYUSHO
发明人： GO MITSUTATSU , RI JUTAKU
IPC分类号： H01L27/14 , H01L21/8252 , H01L27/095 , H01L27/144 , H01L31/10 , H01L31/105 , H01L31/18

49. 发明专利

JPH08241983A HEAT-RESISTANT GATE HETERO STRUCTURE FIELD-EFFECT TRANSISTORAND ITS METHOD 失效
公开(公告)号：JPH08241983A
公开(公告)日：1996-09-17
申请号：JP2988896
申请日：1996-01-24
申请人： MOTOROLA INC
发明人： BAANON PATORITSUKU ONIIRU ZA S , JIYONASAN KEE ABUROKUWA , MAJITSUDO EMU HASEMI , JIENNWA HANGU , BIJIEI KEE NEA , FUARIDE NIKUPOURIAN , SETSUDO NITSUKOO TERANI
IPC分类号： H01L29/41 , H01L21/285 , H01L21/335 , H01L21/338 , H01L21/76 , H01L21/8252 , H01L29/45 , H01L29/47 , H01L29/778 , H01L29/812 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a heterostructure field effect transistor and a manufacturing method, in which the field effect transistor includes at least one passivation layer and an etching prevention layer. SOLUTION: A device with an enhancement mode and/or a depletion mode is realized by changing the process slightly. A metallization step with many suitable features, in which a heat resistant gate 40 and a non-metallic heat resistant ohmic contact 52 are metallized, realizes metallic patterning without using a lift-off method.

50. 发明专利

JPH0864775A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0864775A
公开(公告)日：1996-03-08
申请号：JP16223295
申请日：1995-06-28
申请人： PHILIPS ELECTRONICS NV
发明人： PETERU MIKAERU FUREIRINKU , JIYOZEFU BERAISHI
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/338 , H01L21/8252 , H01L27/095 , H01L29/778 , H01L29/812
摘要： PURPOSE: To position a gate recess to the bottom part of an active layer with precision by performing a non-selective etching up to a depth reference of gate recesses of two transistors, and performing simultaneous non-selective etching with two transistors up to the bottom part level of one transistor gate. CONSTITUTION: Non-selective etching is performed with an active layer 13, as far as a depth 62E equal to the depth difference between gate recesses 52D and 52E of two field effect transistors. Then, in an active layer 13, simultaneous non-selective etching is performed with first and second transistors down to a bottom part level 42D of the gate recess of the first transistor. Thus, a very accurate positioning of the bottom parts 52D and 52E of recesses housing gate contact-point pads 8D and 8E becomes possible. It is positioned without exceeding the allowable error in thickness, which is less than several crystalline single- molecule layers of a semiconductor material.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式