专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明专利

JP2012178795A Transmitter, information processing method, program and transmission system 有权
标题翻译：发射机，信息处理方法，程序和传输系统
公开(公告)号：JP2012178795A
公开(公告)日：2012-09-13
申请号：JP2011041804
申请日：2011-02-28
申请人： Sony Corp , ソニー株式会社
发明人： TAKAHASHI HIROO , LACHLAN BRUCE MICHAEL , YOKOGAWA MINESHI , YOSHIMOCHI NAOKI , OKADA TAKAHIRO
IPC分类号： H04N7/173 , H04H20/28 , H04H20/79 , H04J1/00 , H04J11/00
CPC分类号： H04N5/38 , H04H20/77 , H04L1/0071 , H04L5/0048 , H04N21/2383 , H04N21/6118
摘要： PROBLEM TO BE SOLVED: To easily transmit a signal of a wide band.SOLUTION: A transmitter includes: a first acquiring section acquiring first transmission control information; a second acquiring section acquiring second transmission control information which is the same as information transmitted to another transmission device; and a generating section performing a processing of data being a transmission object in accordance with a parameter included in the first transmission control information and generating data constituted of data of the transmission object to which the processing is performed and of the second transmission control information. This technology can be applied to a transmission device transmitting a signal of DVB-C2.
摘要翻译：要解决的问题：为了容易地发送宽带的信号。解决方案：发射机包括：第一获取部分，获取第一传输控制信息; 第二获取部分获取与发送到另一个传输设备的信息相同的第二传输控制信息; 以及生成部，根据第一发送控制信息中包含的参数，生成数据作为发送对象的处理，生成由执行了处理的发送对象的数据和第二发送控制信息构成的数据。该技术可以应用于传输DVB-C2信号的传输设备。版权所有（C）2012，JPO＆INPIT

42. 发明专利

JP2012085196A Data processor and data processing device 审中-公开
标题翻译：数据处理器和数据处理设备
公开(公告)号：JP2012085196A
公开(公告)日：2012-04-26
申请号：JP2010231197
申请日：2010-10-14
申请人： Sony Corp , ソニー株式会社
发明人： SHINOHARA YUJI , YAMAMOTO MAKIKO , YOKOGAWA MINESHI
IPC分类号： H03M13/19 , H04L27/00 , H04L27/34
CPC分类号： H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2906 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/34
摘要： PROBLEM TO BE SOLVED: To enhance tolerance for error.SOLUTION: An LDPC code having a code length of 4320 bits is written in the column direction of a memory 31, and read in the row direction. The code bits of 2, 4 or 6 bits read from the memory 31 are mapped, as one symbol, to 2, 2or 2signal points. As rearrangement processing for rearranging the code bits of the LDPC code so that a plurality of code bits corresponding to 1 in any one row of the check matrix of the LDPC code are not contained in one symbol, a column twist interleaver performs column twist interleave for changing the start of writing position when the code bits are written in the column direction of the memory 31 for each column of the memory 31. The invention is applicable to transmission of the LDPC code.
摘要翻译：要解决的问题：提高误差容限。解码方法：将码长为4320位的LDPC码写入存储器31的列方向，并在行方向上读取。从存储器31读取的2,4或6位的码位作为一个符号被映射到2 2 ，2 4 < SP>或2 6 信号点。作为用于重新排列LDPC码的码位的重排处理，使得与LDPC码的校验矩阵的任一行对应的多个码位不包含在一个符号中，列扭曲交织器执行列扭转交织当代码位被写入存储器31的每列的存储器31的列方向时，改变写入位置的开始。本发明可应用于LDPC码的传输。版权所有（C）2012，JPO＆INPIT

43. 发明专利

JP2011129974A Receiving apparatus and method, program, and receiving system 有权
标题翻译：接收装置和方法，程序和接收系统
公开(公告)号：JP2011129974A
公开(公告)日：2011-06-30
申请号：JP2009283759
申请日：2009-12-15
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , YUBA TADAAKI , KAWAUCHI TOSHIKI , SAKAI HITOSHI , GOTO TOMONORI , HOCHI TAKU
IPC分类号： H04J11/00
CPC分类号： H04L25/02 , H04L25/0232 , H04L2025/03414
摘要： PROBLEM TO BE SOLVED: To accurately estimate a transmission line even in a frame having a short one-frame length.
SOLUTION: Information of a pilot pattern (PP), NDSYM and FFT size is supplied from an L1 interpretation part 18 to a short frame determination part 14. The short frame determination part 14 determines whether or not a frame in processing is a short frame by using the supplied information and supplies the determination result to a time interpolation part 15. The time interpolation part 15 performs time interpolation by using a pilot corresponding to the determination result supplied from the short frame determination part 14. The pilot to be used for the time interpolation becomes a symbol P2 when the determination result indicates the short frame, or becomes a symbol SP when the determination result indicates that the frame is not a short frame. This invention can be applied to a receiving apparatus for receiving a signal of DVB-T2 standard.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使在具有短的一帧长度的帧中也能精确地估计传输线。解决方案：从L1解释部分18向短帧确定部分14提供导频模式（PP），NDSYM和FFT大小的信息。短帧确定部分14确定处理中的帧是否为通过使用提供的信息进行短帧，并将确定结果提供给时间插值部15.时间插值部15通过使用与从短帧确定部14提供的确定结果相对应的导频来执行时间插值。要使用的导频当确定结果指示短帧时，时间内插成为符号P2，或者当确定结果指示帧不是短帧时，变成符号SP。本发明可以应用于接收DVB-T2标准的信号的接收装置。版权所有（C）2011，JPO＆INPIT

44. 发明专利

JP2011041098A Reception device and method, program, and reception system 有权
标题翻译：接收设备和方法，程序和接收系统
公开(公告)号：JP2011041098A
公开(公告)日：2011-02-24
申请号：JP2009187946
申请日：2009-08-14
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , OKADA SATOSHI
IPC分类号： H04J3/00 , H04N7/173 , H04N21/4385 , H04N21/44 , H04N21/442
CPC分类号： H04N21/4344 , H04N21/4345 , H04N21/4346 , H04N21/4347 , H04N21/6112
摘要： PROBLEM TO BE SOLVED: To avoid a non-output period of a TS.
SOLUTION: A buffer 31 follows write control by a write control section 32 to successively store a PLP to be inputted, and a read rate operation section 33 computes a TS rate based on the PLP to be inputted. A read control section 34 reads the PLP stored in the buffer 31 with a lapse of delay time that is obtained from the PLP to be inputted and delay time operation information and is the time from when Common PLP synchronizes with Data PLP to when the PLP is read, and outputs the TS restored according to the TS rate to a post-stage decoder, thus reliably performing decoding by the decoder. The present invention can be applied to a receiver for receiving a signal in an M-PLP system conforming to DVB-T.2.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：避免TS的非输出周期。解决方案：缓冲器31由写入控制部件32进行写入控制，以连续地存储要输入的PLP，读取速率操作部件33基于要输入的PLP来计算TS速率。读取控制部分34以从输入的PLP获得的经过的延迟时间和延迟时间操作信息读取存储在缓冲器31中的PLP，并且是从公共PLP与数据PLP同步到PLP为止的时间读取并将根据TS速率恢复的TS输出到后级解码器，从而可靠地执行解码器的解码。本发明可以应用于在符合DVB-T.2的M-PLP系统中接收信号的接收机。版权所有（C）2011，JPO＆INPIT

45. 发明专利

JP2010087750A Receiving device and method, and program 有权
标题翻译：接收设备和方法，程序
公开(公告)号：JP2010087750A
公开(公告)日：2010-04-15
申请号：JP2008253299
申请日：2008-09-30
申请人： Sony Corp , ソニー株式会社
发明人： KAWAUCHI TOSHIKI , HATTORI MASAYUKI , MIYAUCHI TOSHIYUKI , YOKOGAWA MINESHI , SHIMIZU KAZUHIRO , FUNAMOTO KAZUHISA
IPC分类号： H04J11/00
CPC分类号： H04L27/2662 , H04L25/0232 , H04L25/03159 , H04L27/2656 , H04L27/2665
摘要： PROBLEM TO BE SOLVED: To change a synchronization method of OFDM symbols depending on a situation. SOLUTION: When a demodulation start signal is input, a symbol position, which is decided by a first symbol position decision section 132, is selected first. When an estimation completion flag indicating that a symbol number has been estimated is supplied, a symbol position, which is decided by a second symbol position decision section 133, is selected next. When capturing of frame synchronization is completed and a frame synchronization flag is supplied, the symbol position, which is decided by a third symbol position decision section 134, is selected. An FFT interval is set based on a symbol synchronization flag indicating a selected position, and FFT is performed to an OFDM time domain signal. The present invention can be applied to a receiving device for receiving OFDM signals. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：根据情况改变OFDM符号的同步方法。解决方案：当输入解调开始信号时，首先选择由第一符号位置决定部分132决定的符号位置。当提供指示已经估计了符号号的估计完成标志时，接下来选择由第二符号位置决定部分133决定的符号位置。当帧同步的捕获完成并且帧同步标记被提供时，选择由第三符号位置决定部分134决定的符号位置。基于指示所选位置的符号同步标记来设置FFT间隔，并且对OFDM时域信号执行FFT。本发明可以应用于接收OFDM信号的接收装置。版权所有（C）2010，JPO＆INPIT

46. 发明专利

JP2010081514A Unit and method for processing information, display device, and program 有权
标题翻译：用于处理信息的单元和方法，显示设备和程序
公开(公告)号：JP2010081514A
公开(公告)日：2010-04-08
申请号：JP2008250285
申请日：2008-09-29
申请人： Sony Corp , ソニー株式会社
发明人： KAWAUCHI TOSHIKI , MIYAUCHI TOSHIYUKI , YOKOGAWA MINESHI , OKAMOTO TAKUYA , KAMATA HIROYUKI
IPC分类号： H04J11/00
CPC分类号： H04L25/0212 , H04L25/022 , H04L25/0232 , H04L27/2647 , H04L27/2665
摘要： PROBLEM TO BE SOLVED: To restrain deterioration in signal quality after FFT processing in OFDM demodulation. SOLUTION: At a symbol synchronization section 15, a tuner receives an OFDM signal transmitted in an OFDM system, an FFT section performs FFT to a signal of an FFT interval in the received OFDM signal, an IFFT section 41 estimates a delay profile from the received OFDM signal, an ISI estimation section 42 uses the estimated delay profile to estimate the amount of ISI to each of a plurality of candidates of the FFT interval, and a minimum value search section 43 searches a candidate, where an estimated amount of ISI is minimized, from the plurality of candidates in the FFT interval to supply the searched candidate to the FFT section as the FFT interval. The present invention can be applied to, for example, an OFDM demodulator. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了抑制OFDM解调中的FFT处理之后的信号质量的劣化。解决方案：在符号同步部分15，调谐器接收在OFDM系统中发送的OFDM信号，FFT部分对所接收的OFDM信号中的FFT间隔的信号执行FFT，IFFT部分41估计延迟分布从所接收的OFDM信号中，ISI估计部分42使用估计的延迟分布来估计FFT间隔的多个候选中的每个的ISI的量，并且最小值搜索部分43搜索候选，其中估计的从FFT间隔中的多个候选者中将ISI最小化，以将搜索的候选提供给FFT部分作为FFT间隔。本发明可以应用于例如OFDM解调器。版权所有（C）2010，JPO＆INPIT

47. 发明专利

JP2009225005A Data processing apparatus, data processing method, and program 有权
标题翻译：数据处理设备，数据处理方法和程序
公开(公告)号：JP2009225005A
公开(公告)日：2009-10-01
申请号：JP2008066090
申请日：2008-03-14
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , YOSHIMOCHI NAOKI , MIYAUCHI TOSHIYUKI , HORIGUCHI TAKASHI , HORI SATORU
IPC分类号： H03M13/39 , H03M13/25 , H04J11/00
CPC分类号： H03M13/41
摘要： PROBLEM TO BE SOLVED: To precisely estimate a data series using a trellis, while reducing the number of surviving states. SOLUTION: A branch metric calculation section 201 calculates branch metric, while limiting the number of branching states to the number of limited states M. A state metric calculation section 202 uses the branch metric to calculate the state metric of a candidate of the surviving state. The minimum detection section 203 detects the minimum state metric of the state metric of a candidate of the surviving state. A path memory 208 stores the state branching from an effective state, namely the state at least truncation length L-1 before, from the state of the minimum state metric, as the surviving state, and selects the candidate of data corresponding to the effective state as the estimate of the data. The present invention can be applied to the estimation of a symbol series. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使用网格精确估计数据序列，同时减少幸存状态的数量。解决方案：分支度量计算部分201计算分支度量，同时将分支状态数量限制为限制状态数量M.状态度量计算部分202使用分支度量来计算候选人的状态度量幸存状态最小检测部分203检测剩余状态的候选者的状态度量的最小状态度量。路径存储器208将从最小状态度量状态起的有效状态（即至少截断长度L-1的状态）的状态分支为存活状态，并且选择对应于有效状态的数据候选作为数据的估计。本发明可以应用于符号序列的估计。版权所有（C）2010，JPO＆INPIT

48. 发明专利

JP2009224820A Encoder and encoding method 审中-公开
标题翻译：编码器和编码方法
公开(公告)号：JP2009224820A
公开(公告)日：2009-10-01
申请号：JP2008052268
申请日：2008-03-03
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , YAMAMOTO MAKIKO , OKADA SATOSHI , SAKAI RUI
IPC分类号： H03M13/19
CPC分类号： H03M13/1102
摘要： PROBLEM TO BE SOLVED: To provide an LDPC (Low Density Parity Check) code having satisfactory performance. SOLUTION: An encoding processing section 601 performs encoding by the LDPC code having, for example, an encoding length of 64,800 bits and an encoding rate of 3/5. The inspection matrix of the LDPC code is composed by arranging one element of an information matrix that indicates the position of the one element of the information matrix corresponding to information length according to the encode length and the encoding rate of the inspection matrix for each 360 rows and is decided by an inspection matrix initial value table at a period for each 360 rows in a row direction. The inspection matrix initial value table differs from that prescribed by the standard of DVB-S. 2. The present method can be applied to an encoder for LDPC encoding. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有令人满意的性能的LDPC（低密度奇偶校验）码。解决方案：编码处理部分601通过具有例如64,800位的编码长度和3/5的编码速率的LDPC码执行编码。 LDPC码的检查矩阵通过根据编码长度和针对每360列的检查矩阵的编码率排列指示信息矩阵的一个元素的位置对应于信息长度的信息矩阵的一个元素并且由行方向上的每360行的周期的检查矩阵初始值表决定。检查矩阵初始值表与DVB-S标准规定的不同。本方法可以应用于用于LDPC编码的编码器。版权所有（C）2010，JPO＆INPIT

49. 发明专利

JP2009182552A Decoding device and method, receiving device and method, and program 有权
标题翻译：解码设备和方法，接收设备和方法以及程序
公开(公告)号：JP2009182552A
公开(公告)日：2009-08-13
申请号：JP2008018536
申请日：2008-01-30
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , IIDA YASUHIRO , MIYAUCHI TOSHIYUKI , HAGIWARA TAKASHI , MINAMINO TAKANORI , HANEDA NAOYA
IPC分类号： H04L27/38 , H04L7/00 , H04L27/22
CPC分类号： H04L27/3827 , H04L1/0054 , H04L1/208 , H04L7/042
摘要： PROBLEM TO BE SOLVED: To allow quick synchronization even when a frequency spectrum is inverted. SOLUTION: A coded data decoding part 17 decodes demodulated data which is obtained by demodulating an orthogonal demodulated signal arising from digital modulation of a carrier and is composed of in-phase axis data and orthogonal axis data, to generate decoded data C1 and decodes demodulated data obtained by interchanging the in-phase axis data and the orthogonal axis data of the decoded data C1, to generate decoded data C2, and a synchronization detector 19 detects a synchronizing word from serial data D1 corresponding to the decoded data C1 and detects a synchronizing word from serial data D2 corresponding to the decoded data C2 and selects and outputs one of serial data D1 and serial data D2 on the basis of the detection result. This invention is applicable to a decoding device which detects synchronization by decoding demodulated data resulting from demodulating a quadrature modulated signal obtained by digital modulation of a carrier. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使当频谱反转时也允许快速同步。编码数据解码部17对通过解调由载波的数字调制产生的正交解调信号而得到的解调数据进行解码，由同相轴数据和正交轴数据构成，生成解码数据C1，解码通过交换同步轴数据和解码数据C1的正交轴数据而获得的解调数据，以产生解码数据C2，并且同步检测器19检测与解码数据C1相对应的串行数据D1中的同步字，并检测来自与解码数据C2对应的串行数据D2的同步字，并根据检测结果选择并输出串行数据D1和串行数据D2之一。本发明可应用于通过对通过对载波的数字调制获得的正交调制信号进行解调得到的解调数据进行解码来检测同步的解码装置。版权所有（C）2009，JPO＆INPIT

50. 发明专利

JP2009027302A Decoder and decoding method 有权
标题翻译：解码和解码方法
公开(公告)号：JP2009027302A
公开(公告)日：2009-02-05
申请号：JP2007186565
申请日：2007-07-18
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , SHINTANI OSAMU
IPC分类号： H03M13/19
摘要： PROBLEM TO BE SOLVED: To reduce a circuit scale without deteriorating decoding performance in decoding a LDPC (Low Density Parity Check) code. SOLUTION: An input buffer 513 temporarily stores reception values of intermittently input LDPC codes and continuously reads the stored reception values. A reception value memory 601 of a connection memory 514 stores the reception values continuously read by the input buffer 513 and reads every P stored reception values. A calculating part decodes every P reception values which are read for P reception values by the reception value memory 601. A message memory 602 of the connection memory 514 stores messages being halfway results of decoding, reads every P stored messages and outputs them to the calculating part. Further, the bit width of the input buffer 513 is smaller than the bit width of the connection memory 514. This invention is applicable, for example, to a tuner for receiving satellite broadcasting. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：在解码LDPC（低密度奇偶校验）码的同时降低电路规模而不降低解码性能。解决方案：输入缓冲器513临时存储间歇输入的LDPC码的接收值，并连续读取存储的接收值。连接存储器514的接收值存储器601存储由输入缓冲器513连续读取的接收值，并读取每个P个存储的接收值。计算部分对由接收值存储器601读取的P个接收值的每个P个接收值进行解码。连接存储器514的消息存储器602存储作为解码结果的一半的消息，读取每个P个存储的消息，并将它们输出到计算部分。此外，输入缓冲器513的位宽小于连接存储器514的位宽度。本发明可以应用于例如用于接收卫星广播的调谐器。版权所有（C）2009，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式