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    • 42. 发明专利
    • METHOD FOR REFINING DATA FOR SIMILARITY DISCRIMINATION AND DEVICE FOR PERFORMING THE METHOD
    • JPH07302265A
    • 1995-11-14
    • JP9601194
    • 1994-05-10
    • NIPPON TELEGRAPH & TELEPHONE
    • MATSUZAWA KAZUMITSUKASAHARA KANAMEYUGAWA TAKASHIISHIKAWA TSUTOMU
    • G06F17/30
    • PURPOSE:To refine data for similarity discrimination by considering noticed attributes as elements, multiplying predetermined weighting values by respective importance degrees and adding multiplied results to the attribute sets of the elements for the respective noticed attributes forming pairs with the importance degrees of a value equal to or more than a predetermined value. CONSTITUTION:For the data 1 for the similarity discrimination, the data for the similarity discrimination before refining stored in a data base are expressed in a chart form and the attribute sets 3 which are the sets of the pairs of the attributes and the importance degrees are made correspond to the elements 2. The attributes for which the importance degree of the attribute set of the element A is equal to or more than 0.5, that are the attribute B and the attribute C, are defined as the noticed attributes 4. The attribute B and the attribute C which are the noticed attributes are respectively considered as the elements and the corresponding attribute sets are searched from the data for the similarity discrimination. The importance degrees are multiplied by 0.8 which is a specified value 5 and 0.5 which is the value 6 and added to the attribute set of the original element A, the attribute set of the element A is newly defined. A similar operation is repeated for the elements other than the element A and storage in the data base is performed.
    • 48. 发明专利
    • INTER-PROCESSOR SYNCHRONIZING SYSTEM
    • JPS62134752A
    • 1987-06-17
    • JP27471785
    • 1985-12-06
    • NIPPON TELEGRAPH & TELEPHONE
    • KOBAYASHI MASAMITSUMOMOI SHIGEHARUISHIKAWA TSUTOMU
    • G06F15/16G06F15/177
    • PURPOSE:To speed up synchronization of all processors, and to execute an inter-processor synchronization at a high speed by generating a synchronizing signal by executing an access to a specified memory address of each processor, and setting a signal in case synchronizing signals of all processors have coincided, as a response signal of a memory of each processor. CONSTITUTION:In case a synchronization between processors is required, a CPU 21 issues artificially a memory access instruction to a specified address which does not exist on a memory 22, outputs a request signal to a request line 213, and loads its specified address on a data line 212. A decoder 23 is started by the request signal of the request line 213, and when the data line 212 shows a specified address, a synchronizing signal is outputted. Such a synchronizing signal is held by a latching circuit 24, and also sent out to a coincidence detecting circuit 5 through a synchronizing output line 214. At the time of the synchronizing operation, the same operation is executed by other processor, as well, and the synchronizing signals are sent out to the coincidence detecting circuit 5.