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41. 发明专利

JPH08172349A STATIC LOGIC CIRCUIT 失效
公开(公告)号：JPH08172349A
公开(公告)日：1996-07-02
申请号：JP26879695
申请日：1995-10-17
申请人： HITACHI LTD
发明人： KANEKO KENJI , HANAWA MAKOTO , SHIMADA KENTARO , NAKAJIMA KAZUNORI
IPC分类号： H03K19/173 , H03K19/017 , H03K19/0948
摘要： PURPOSE: To increase operation speed and to reduce power consumption by adopting discharge compensating logic gates and charge compensating type logic gates and alternately cascade-connecting these two kinds of logic gates to constitute required logic operation. CONSTITUTION: A discharge compensating logic gate 21 having a NAND function, a charge compensating logic gate 22 having a NOR function, a discharge compensating logic gate 23 having the NOR function, and a charge compensating logic gate 24 having the NAND function are cascade-connected to constitute a logic gate string A in which the logic gate on the foretmost stage is the discharge compensating type. Un the other hand, a charge compensating type logic gate 25 having the NAND function, a discharge compensating logic gate 26 having the NOR function, a charge compensating logic gate 27 having the NOR function, and a discharge compensating logic circuit 28 having the NAND function are cascade-connected to constitute a logic gate string B in which the logic gate on the foremost stage 15 the charge compensating type. The output terminals of both the strings A, B are connected to a signal synthesizing circuit 20. The circuit 20 synthesizses the output signals from the two logic gate strings A, B and extracts an output signal obtained by speeding up the rise and fall transition time of input signals supplied to the foremost stage logic gates.

42. 发明专利

JPH07168714A DIGITAL SIGNAL PROCESSOR AND METHOD FOR EXECUTING INSTRUCTION USING THE SAME 失效
公开(公告)号：JPH07168714A
公开(公告)日：1995-07-04
申请号：JP22856194
申请日：1994-09-26
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , UMAJI TORU , NAKAGAWA TETSUYA , KANEKO KENJI
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
摘要： PURPOSE:To provide a digital signal processor(DSP) for defining the same data processing or data transfer operation and the DSP for executing a RISC class instruction. CONSTITUTION:A DSP 1100 is composed of an instruction memory 1400 and an instruction decoder 1600. The instruction memory 1400 stores the sequence of instruction words including a DSP instruction word and a RISC instruction word. Each instruction word is provided with a type code field TY for designating whether the instruction is a RISC instruction or a DSP instruction. The prescribed RISC instruction word is provided with a different source and a destination field for designating register positions for a data source and a data destination. One of the source and the destination field in the prescribed RISC instruction word is provided with bits more than those of a correspondent field in the prescribed DSP instruction word at least.

43. 发明专利

JPH06224691A RESISTANCE CIRCUIT AND FILTER CIRCUIT USING THE SAME 失效
公开(公告)号：JPH06224691A
公开(公告)日：1994-08-12
申请号：JP27337793
申请日：1993-11-01
申请人： HITACHI LTD
发明人： KANEKO KENJI , TAKAGI KATSUAKI , MATSUURA TATSUJI , HAGIWARA YOSHIMUNE
IPC分类号： H03H7/06 , H03H11/04 , H03L7/107
摘要： PURPOSE:To vary the resistance value on an integrated circuit by a voltage and to use it to automatically vary the time constant of a filter circuit. CONSTITUTION:This resistance circuit is provided with a constant current source Ix controlled by a voltage, a voltage generating circuit which generates a voltage proportional to the current of the constant current circuit by first and second terminals of a three-terminal element, a three-terminal element operated as a MOS diode, and a circuit where three-terminal elements operated in a constant current are connected in series, and the voltage of the voltage generating circuit is supplied to the series connection circuit to vary the impedance at both ends of the series connection circuit. Thus, a large resistance value is obtained in a small element area.

44. 发明专利

JPH0574969B2 失效
公开(公告)号：JPH0574969B2
公开(公告)日：1993-10-19
申请号：JP23315284
申请日：1984-11-07
申请人： HITACHI LTD
发明人： NAKAGAWA TETSUYA , KANEKO KENJI , HAGIWARA YOSHIMUNE , MATSUSHIMA HITOSHI , UEDA HIROTADA
IPC分类号： H03K19/20 , G06F7/501 , G06F7/53 , H03K19/0948 , G06F7/50

45. 发明专利

JPH0425708B2 失效
公开(公告)号：JPH0425708B2
公开(公告)日：1992-05-01
申请号：JP16483582
申请日：1982-09-24
申请人： HITACHI LTD
发明人： OGURA SADAO , KANEKO KENJI
IPC分类号： H01L27/082 , H01L21/8226 , H01L27/02 , H03K19/091

46. 发明专利

JPH0258132A LANGUAGE PROCESSOR 失效
公开(公告)号：JPH0258132A
公开(公告)日：1990-02-27
申请号：JP20833288
申请日：1988-08-24
申请人： HITACHI LTD
发明人： SHINODA YOSHIHIRO , NARUSHIMA MASACHIKA , YABE EIICHI , KIKUCHI AKIRA , KANEKO KENJI
IPC分类号： G06F15/16 , G06F9/45
摘要： PURPOSE:To easily generate an object program even when a source program for a multiprocessor system is coexisted and described by recognizing a control instruction included in the inputted source program and executing a processing to obtain the object program. CONSTITUTION:Plural processing means 2 and 3, which fetch a source program 5 described with the coexistence of a sub-program corresponding to each processor and execute processings to obtain an object program 6 from the sub-program at every processor to be operated by the sub-program, and a control means 1, which designates the processing means 2 and 3 to process the sub-program based on information such as a control instruction written on the sub-program, are provided. Thus, even when the source programs 5 for the multi-processor system are coexisted and described without making them independent at every processor, the object program 6 can be easily generated based on them.

47. 发明专利

JPH01237766A DATA PROCESSOR AND PICTURE DATA PROCESSING SYSTEM USING DATA PROCESSOR 失效
公开(公告)号：JPH01237766A
公开(公告)日：1989-09-22
申请号：JP6324088
申请日：1988-03-18
申请人： HITACHI LTD
发明人： SAGESAKA YASUHIRO , KANEKO KENJI , NAKAGAWA TETSUYA , MIYAMOTO MASABUMI , HAGIWARA YOSHIMUNE
IPC分类号： G06F17/10 , G06T1/20
摘要： PURPOSE:To attain high speed arithmetic for the data of double accuracy by executing the prescribed connection of a data bus to a multiplexer for arithmetic and logic operation and selecting the data bus, etc., in a picture data system to execute the multiplication logic operation and multiplication processing of (n)-bit picture data. CONSTITUTION:The (n)-bit data from a data memory bank 104 through an (n)-bit data transferring bus 122 and 2n-bit output data from a general register 106 are inputted to a multiplexer 107. Then, the (n)-bit data through (n)-bit data transferring buses 121-123 and the 2n-bit data from an output register 110 of a multiplied result are added to a multiplexer 108. The outputs of these multiplexers 107 and 108 are obtained as an input and the arithmetic processing is executed by a arithmetic and logic computing element 105. For these multiplexers 107 and 108, a control signal 130 is controlled and the (n)-bit data or the 2n-bit data are selected and outputted. Then, without using the 2n-bit data through the register 110, the arithmetic and logic operation of the double accuracy data by the 2n-bit data can be executed at a high speed with one machine cycle.

48. 发明专利

JPH01166221A INFORMATION PROCESSOR 失效
公开(公告)号：JPH01166221A
公开(公告)日：1989-06-30
申请号：JP32411287
申请日：1987-12-23
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , KANEKO KENJI , NAKAGAWA TETSUYA , UEDA HIROTADA , HAGIWARA YOSHIMUNE
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/38
摘要： PURPOSE:To improve information processing ability by dividing all control functions into those having the long periods of executing time and others having the short periods respectively and validating the field where the control functions of long periods are described at every other fixed interval of a program address space. CONSTITUTION:An instruction code 201 is divided into a 1st field 202 and a 2nd field 203. The control functions having the short period of executing time are described in the field 202 together with the control functions having the long periods described in the field 203 respectively. Thus the instruction executing intervals are different from each other at every field and therefore the address signals 112 and 113 supplied to address decoders 103 and 104 respectively have different types from each other. Furthermore the instruction codes 116 and 117 have different types of instruction executing timing for separate production of timing signals 115 and 114 respectively. In such a way, the executing speeds can be set at every field and therefore the overall processing speed is increased even with a parallel working processor having a long horizontal instruction code.

49. 发明专利

JPS63168045A GATE PROTECTIVE CIRCUIT 失效
公开(公告)号：JPS63168045A
公开(公告)日：1988-07-12
申请号：JP31313086
申请日：1986-12-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIDA JUN , KANEKO KENJI , KIUCHI ATSUSHI , HAGIWARA YOSHIMUNE , UEDA HIROTADA
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/088
摘要： PURPOSE:To prevent the electrostatic breakdown of gates by utilizing the ON resistances of MOSFETs. CONSTITUTION:Elements N1 and N2 are longitudinally connected, a MOSFET M1 or M2 is turned-ON according to whether the input potential of the N1 is high or low and the inverted signal of input is turned input to the gates of MOSFETs M3 and M4. The input to the gates of the M3 and the M4 has the ON resistances of the M1 and the M2 of several kOMEGA and these have a role for protecting the gates. The elements N1 and N2 are valid for an arbitrary logical element and the need to provide an exclusive protection against the inputs of the longitudinally connected elements in an integrated circuit is eliminated. Accordingly, the circuit to utilize the ON resistances of the MOSFETs has inevitably a function for protecting the gates from the viewpoint of its structure.

50. 发明专利

JPS63118878A LSI DESIGNING DEVICE 失效
公开(公告)号：JPS63118878A
公开(公告)日：1988-05-23
申请号：JP26373786
申请日：1986-11-07
申请人： HITACHI LTD
发明人： ISHII NAOKO , KANEKO KENJI , TAKAGI KATSUAKI , AOKI MASAO , MASUDA HIROO , MATSUO HITOSHI , SHIMADA SHOZO
IPC分类号： H03K19/00 , G06F17/50 , H01L21/82
摘要： PURPOSE:To design an LSI satisfying characteristic specifications in a short time by applying an optimum designing method to a logical design and function design that require extremely labor and time. CONSTITUTION:LSI characteristics (y) is approximated by a function formula including a design parameter (x) and the optimum design parameter satisfying the target specifications is extracted out of said function formula by a design means. A CAD system applying the maximum design parameter comprises a simulation means for timing, logic and function designs that require the largest manpower and the longest design period. Thus the LSI designing manpower and designing period are extraordinarily reduced. In this system, P pairs of LSI characteristics are obtained with respect to P pairs of design parameters given in the form of a design matrix produced by desired procedures. Thus a LSI characteristic simulator group is carried out by P times. Based on these execution results, a model parameter is produced for a function approximating expression of the characteristic (y) to the parameter (x).

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