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31. 发明专利

JPH0580175B2 失效
公开(公告)号：JPH0580175B2
公开(公告)日：1993-11-08
申请号：JP15693582
申请日：1982-09-09
申请人： SEIKO EPSON CORP
发明人： HASHIMOTO MASAMI , YAMADA ICHIRO
IPC分类号： H03K21/02 , H03K23/54

32. 发明专利

JPH05236763A 失效
公开(公告)号：JPH05236763A
公开(公告)日：1993-09-10
申请号：JP31588891
申请日：1991-11-29
申请人： NEC CORP
发明人： MATSUSHIMA OSAMU
IPC分类号： H02M7/537 , H02P27/08 , H03K17/08 , H03K17/66 , H03K23/54 , H02P7/63
摘要： PURPOSE:To protect transistors against breakdown due to abnormal driving pulse output in a transistor power amplifier circuit of bridge connection. CONSTITUTION:The pulse drive circuit comprises an interruption logic detecting circuit 37 comprising edge detecting circuits 35, 36 for detecting interruption logic and logic gates E31-E33, a timer 31 for counting the detecting interval of interruption logic, a latch circuit 32 for latching the count of the timer 31, a comparison register 34 for storing comparision values, and a circuit 33 for comparing the count with the comparison value.

33. 发明专利

JPH0595281A STATIC TYPE CLOCKED CMOS FREQUENCY DIVIDER 失效
公开(公告)号：JPH0595281A
公开(公告)日：1993-04-16
申请号：JP25378691
申请日：1991-10-01
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YAMAMOTO YASUSUKE
IPC分类号： H03K23/00 , H03K23/54
摘要： PURPOSE:To obtain the clocked CMOS frequency divider operated at a higher speed than that of a dynamic type frequency divider regardless of the static type frequency divider. CONSTITUTION:A memory function by inverters V1, V2 or V3, V4 is added to two high speed dynamic frequency dividers being a dynamic frequency divider comprising CL1, CL2 and other dynamic frequency divider comprising CL3, CL4. Thus, the static operation compatible with a low speed operation is attained and the output data of each frequency divider are used for other input data by cross-coupling to reduce the number of gates included in a path (critical path) whose signal propagation delay time is longest.

34. 发明专利

JPH04299614A COUNTER 失效
公开(公告)号：JPH04299614A
公开(公告)日：1992-10-22
申请号：JP6433091
申请日：1991-03-28
申请人： ASAHI CHEMICAL MICRO SYST
发明人： TAJIRI KATSUHIRO , IWAMOTO SHIGENARI
IPC分类号： H03K23/54
摘要： PURPOSE:To reduce noise due to state transition of an FF by devising the bit state to be transited only by a 2-bit Johonson count at maximum in the case of counting the counter. CONSTITUTION:Two-bit Johonson counters 1, 2 are connected in series to form a 4-bit counter. The count is started at RST=H and the count is started at a trailing of a reference clock CLK. Outputs A1, A0 of the counter 1 are counted as 00, 01, 11, 10... and when the output of the output A1 is 10, the count is carried to the counter 2 at the leading of the reference clock CLK and the counter 2 starts counting. When an inverse of output A1 of a DFF 11 is used for a reference clock of DFFs 12, 13, the state of outputs A3, A2 of the counter 2 is similarly transited as 00, 01, 11, 10.... A maximum of 2-bit is transited simultaneously in the outputs A0-A3. A maximum of N bits is changed for simultaneously in the 2N-bit counter. Thus, noise such as ripple or the like due to state change is reduced.

35. 发明专利

JPH04195999A SEQUENTIAL LOGIC CIRCUIT 失效
公开(公告)号：JPH04195999A
公开(公告)日：1992-07-15
申请号：JP32707790
申请日：1990-11-28
申请人： FUJITSU LTD
发明人： TAKATSU MOTOMU
IPC分类号： G06F7/00 , G05B19/07 , G11C19/28 , H03K3/36 , H03K19/21 , H03K23/54
摘要： PURPOSE:To attain a high-speed operation with less number of active elements by cascade-connecting plural stages of a state-maintaining circuits and inputting clock signals in the other plural ends of the input terminals of each state- maintaining circuit. CONSTITUTION:An inversion output type 2 input state maintaining circuits 11-15 are cascade-connected only plural stages, and plural input terminal ends A of each of the state-maintaining circuits 11-15 are connected to the output terminals Q of each preceding stage of the state maintaining circuits. And, an input signal D is inputted into the one input terminal ends A of a first level of the state maintaining circuit 11, the input terminal ends A of a second stage through a last stage of the state-maintaining circuits 12-15 are connected to the output terminals Q of each of the preceding stages of the state maintaining circuits, and from the output terminals Q of the last stage of the state maintaining circuit 15, an output signal Q is outputted. In the opposite input terminal ends B of each state maintaining circuit 11-15, a common clock signal C is inputted. Thus, the sequential logic circuit is composed of less number of active elements, and the high-speed operation is made possible.

36. 发明专利

JPH0410811A LOW NOISE COUNTER AND IMAGE PICKUP DEVICE PROVIDED WITH THE SAME 失效
公开(公告)号：JPH0410811A
公开(公告)日：1992-01-16
申请号：JP11313890
申请日：1990-04-27
申请人： SANYO ELECTRIC CO
发明人： HIGASHITSUTSUMI YOSHIHITO
IPC分类号： H04N5/06 , H03K23/54 , H03K23/64 , H04N5/335 , H04N5/341 , H04N5/365 , H04N5/372 , H04N5/376 , H04N5/378
摘要： PURPOSE:To reduce periodic noise due to the operation of the circuit by providing a common clock having a prescribed period to each shift register to synchronize the operation of each shift register with the clock. CONSTITUTION:The outputs Q of flip-flops 10d, 11d, 12d, at the final stage are supplied respectively to the input T of flip-flops 10a, 11a, 12a of the first stage. Moreover, processing of ORs 13, 14 between the output Q of flip-flops 10c, 11c at the 3rd stage of Johnson counters 7, 8 and the output Q of the flip- flops 10d, 11d at the final stage is outputted as carry signals RCO1, RCO2. Thus, the basic clock CLK is supplied to the timing input T of the flip-flops 10a-10d of the Johnson counter 7 via a buffer to obtain the equal delay with that of a logic gate in order to make matching with the operation of other Johnson counters 8, 9. Thus, power noise due to the operation of the counter circuits is reduced.

37. 发明专利

JPH03263920A COUNTER CIRCUIT 失效
公开(公告)号：JPH03263920A
公开(公告)日：1991-11-25
申请号：JP6304290
申请日：1990-03-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： IKEDA KANICHIRO , SEGAWA KAZUAKI
IPC分类号： H03K23/54
摘要： PURPOSE:To accelerate the operating speed of this counter circuit by assembling the NOT gate of a feedback gate in a D-FF in a veritically laminated gate, and operating it with the same constant current source as that for a clock input terminal. CONSTITUTION:The counter circuit is the one of four bit operation and is composed of three D-FFs 1 and a feedback NOR gate, and ordinary D-FFs are used as the D-FFs at second and third stages. Unified elements 2 are used as the NOR gate and the D-FF at the initial stage. The assembling of the NOR gate in the D-FF is performed by using an SCFL circuit used in a GaAs IC, etc., and the vertically laminated gates are used as an E-FET 7a for input for the NOR gate and an E-FET for clock input for the D-FF, and they are operated with the same current source. Therefore, the delay time of a NOR gate assembling D-FF is almost equal to that of a single D-FF. Consequently, the delay time for entire circuit can be shortened by nearly delay time of one NOR gate.

38. 发明专利

JPH02226813A PROGRAMMABLE LOGIC DEVICE HAVING A PLURALITY OF LOGIC ARRAYS ARRANGED INTO MOSAIC LAYOUT WITH A PLURALITY OF INTERFACE BLOCKS IN MIXED ARRANGEMENT 失效
公开(公告)号：JPH02226813A
公开(公告)日：1990-09-10
申请号：JP34507789
申请日：1989-12-28
申请人： SGS THOMSON MICROELECTRONICS
发明人： MIRERA BENEDETSUTEI , ANTONIO KIRIATSUTEI , BINSENTSUO DANIERE , BIAGIO JIYAKAROONE
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K23/54
摘要： PURPOSE: To make needless a pad or an output pin for integrated device for signal feedback by forming a mosaic of memory cell arrays programmable a device system and plurifunction stationary circuit blocks(PSB). CONSTITUTION: A logic device having a network of memory cell arrays has four arrays A1 to A4 of other memory cells which gridirons and separately programmable by changing their conductivity, memory cells are preferably EPROM or EEPROM type, and four arrays A1 to A4 are formed as 'mosaic' together with the fixed number of PSB1-120 Then, OR array is directly cascaded from an AND array, and the output signal of the AND array can be utilized only in non-inverted form and cannot be utilized in inverted form. Thus, many feedback or internal paths for signal can be formed without a pin or a pad for integrated device.

39. 发明专利

JPH02222323A COUNTER CIRCUIT 失效
公开(公告)号：JPH02222323A
公开(公告)日：1990-09-05
申请号：JP4375189
申请日：1989-02-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： TASHIRO SHINICHI , SONE KENRO , OMAE MASANORI
IPC分类号： H03K23/54 , H03K23/40
摘要： PURPOSE:To prevent a noise caused by a frequency dividing circuit of a solid- state image pickup device by roughly equalizing the wiring capacity between flip-flops in a Johnson counter. CONSTITUTION:Each flip-flop FF1-FF101 of a Johnson counter constituted of plural pieces of flip-flops FF1-FF101 is coupled by connection wiring layers whose wiring capacity is roughly equal. By this coupling, loads by the wiring capacity applied to a Q output of each flip-flop FF1-FF101 become equal, and a noise level by a variation of the current consumption at the time of a variation of a Q output logical level of each flip-flop FF1-FF101 always becomes constant. In such a way, a noise caused by a counter circuit in a driving pulse circuit of a solid-state image pickup device can be prevented.

40. 发明专利

JPH01232827A RING COUNTER DEVICE 失效
公开(公告)号：JPH01232827A
公开(公告)日：1989-09-18
申请号：JP5970788
申请日：1988-03-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： IKEDA HIROYUKI , MASUDA NOBUKO , NAGAO AKIFUMI
IPC分类号： H03K23/54 , H03K21/40
摘要： PURPOSE:To restore the erroneous sequence caused by the effect of noise or the like automatically into the normal sequence with simple circuit constitution by providing a reset circuit detecting the malfunction of a ring counter and restoring its operation to the normal operation. CONSTITUTION:A twist ring counter circuit 1 consists of 8-stage of flip-flops 11-18. A malfunction detection circuit 2 consists of logic gate circuits 21-25, selects only the output of a proper flip-flop less than the output of all stages of the twist ring counter circuit 1, thereby detecting malfunction. The reset circuit 3 restores the erroneous sequence of the twist ring counter circuit into the normal sequence.

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