专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明专利

JPH04226083A CONDUCTIVITY MODULATION TYPE MOSFET 失效
公开(公告)号：JPH04226083A
公开(公告)日：1992-08-14
申请号：JP10424191
申请日：1991-05-09
申请人： TOSHIBA CORP
发明人： NAKAGAWA AKIO , WATANABE KIMINORI
IPC分类号： H01L29/78 , H01L29/06 , H01L29/739
摘要： PURPOSE:To provide the title device which generates no latch-up up to a large current region. CONSTITUTION:In a conductivity modulation type MOSFET where p-type base layers 13 and n type emitter layers 14 are formed in a high-resistance n type base layer 12 by DSA process with a gate electrode 16 formed gate insulating film 15 in a region sandwiched by the n type emitter layer 14 and the n type base layer 12 of a p-type base layer 13, a plurality of p-type base layers 13 are arrayed in a zigzag pattern.

32. 发明专利

JPH04137563A PLANAR ELEMENT OF HIGH BREAKDOWN STRENGTH 失效
公开(公告)号：JPH04137563A
公开(公告)日：1992-05-12
申请号：JP25695690
申请日：1990-09-28
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732 , H01L29/78
摘要： PURPOSE:To miniaturize a planar element of high breakdown strength, by so forming a highly resistive film as to be in contact with one end of a polycrystalline silicon film so arranged as to be simultaneously in contact with a source layer and a base layer, and one end of a polycrystalline silicon film so arranged as to be in contact with a drain layer. CONSTITUTION:When a voltage is applied across a source and a drain, the potential of a semiinsulative polycrystalline silicon film 23 is excellently fixed, in such a manner that the drain side is fixed to a drain potential via a p type polycrystalline silicon film 31, and the source side is fixed to a source potential via an n type poly-crystalline silicon film 32. A very weak current flows in the semiinsulative polycrystalline silicon film 23 so as to uniformly distribute all over the element, and uniform potential gradient is generated in the lateral direction. As a result, electric field concentration inside the element is relieved, and a high voltage is obtained. The length of a gate electrode 18 can be an irreducible minimum, and the element length is reduced, thereby the element is miniaturized, and the element length is shortened, so that the resistance in the lateral direction is reduced and the ON resistance is lowered.

33. 发明专利

JPH03211771A CONDUCTIVITY-MODULATION MOSFET 失效
公开(公告)号：JPH03211771A
公开(公告)日：1991-09-17
申请号：JP564090
申请日：1990-01-12
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI , YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO
IPC分类号： H01L29/78 , H01L29/06 , H01L29/739
摘要： PURPOSE:To prevent the concentration of current and latch-up by providing a source layer around a striped drain layer, wherein the drain-source spacing is greater in the edge portions of the striped drain than in the other portions. CONSTITUTION:An n-type base layer and a drain layer 16 in it are formed in a stripe pattern and divided into three parts. A source layer 13 is formed around the base and drain layers. in this striped area, a relation b>a is determined where (a) and (b) are the drain-source spacing in the linear and edge portions of the stripe pattern, respectively. In this conductivity-modulation MOSFET, the lateral distribution of resistor of the n-type base layer is greater in the edge portions than in the linear portions. Therefore, the distribution of hole current in the n-type base layer is substantially uniform although the source layer 13 faced with the drain layer 16 has longer sides in the edge portions. Thus, the concentration of current in the edge portion is reduced compared with the conventional device.

34. 发明专利

JPS62283669A CONDUCTIVITY MODULATION TYPE MOSFET 失效
公开(公告)号：JPS62283669A
公开(公告)日：1987-12-09
申请号：JP12761486
申请日：1986-06-02
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO , WATANABE KIMINORI
IPC分类号： H01L29/68 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/78
摘要： PURPOSE:To improve the load shortcircuit resistance of a conductive modulation type MOSFET by forming the channel length of a channel region formed on a base layer interposed between a source layer and a high resistance layer directly under a gate electrode, the width of the gate electrode and the width of the high resistance layer interposed between a drain layer and the base layer in specific sizes, respectively. CONSTITUTION:A high resistance layer 13 is formed through a buffer layer 12 on a drain layer 11, and a gate electrode 15 is formed by a polycrystalline silicon film through a gate insulating film 14 on the layer 13. The electrode 15 is formed in a lattice shape having a stripelike gap 16. With the electrode 15 as a mask an impurity is diffused to form a base layer 17 and a source layer 18, and a channel region 19 is formed on the layer 17 interposed between the layers 18 and 13. In such a structure, a channel length l is set to 5.5mum, a gate electrode length LG is set to 30mum or longer, and the width Wn of the layer 13 is set to 120mum or longer. Thus, a latchup current can be increased without raising an ON voltage by the optimum design of an element parameter.

35. 发明专利

JPS62229977A MANUFACTURE OF CONDUCTION-MODULATION MOSFET 失效
公开(公告)号：JPS62229977A
公开(公告)日：1987-10-08
申请号：JP7115986
申请日：1986-03-31
申请人： TOSHIBA CORP
发明人： NAKAGAWA AKIO , WATANABE KIMINORI , YAMAGUCHI YOSHIHIRO
IPC分类号： H01L29/68 , H01L21/331 , H01L21/336 , H01L29/78
摘要： PURPOSE:To manufacture a conduction-modulation MOSFET having excellent characteristics at a high yield by a method wherein a high-impurity concentration layer, which brings a base layer into a low-resistance state and is used for preventing a latch-up, is formed at the central part of the base layer in a self-matching manner. CONSTITUTION:Gate electrodes 51 consisting of a poly Si film are formed on the substrate of a structure; wherein an n-type high-resistance layer 3 is formed on a p drain layer 1 through an n buffer layer 2; through a gate insulating film 4. After this, masking materials 6 for covering the intervals between the gate electrodes 51 and first masking materials 52 are formed of a photo resist, for example, and boron, for example, is ion-implanted to form a p layer 7. After a heat treatment is performed and activation and diffusion of the impurity of the p layer 7 are performed, an impurity is doped using the gate electrodes 51 as masks to form a p-type base layer 8 and moreover, a mask is formed on the central part of the p-type base layer 8 and an impurity is doped using this mask and the gate electrodes 51 as masks to form n source layers g. Thereby, the p layer 7 for bringing the p-type base layer 8 into a low-resistance state can be formed at the center of the p-type base layer 8 in a slef-matching manner.

36. 发明专利

JPS6211272A HIGH DIELECTRIC STRENGTH PLANAR TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6211272A
公开(公告)日：1987-01-20
申请号：JP14923985
申请日：1985-07-09
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI , NAKAGAWA AKIO
IPC分类号： H01L29/06 , H01L29/10 , H01L29/40 , H01L29/78
摘要： PURPOSE:To obtain a small-size high dielectric strength device by a method wherein P-type guard rings and an N type layer surrounding the guard rings are provided on an N-type Si substrate and a high resistance layer is provided on an insulator between them. CONSTITUTION:P type protection rings 16 are formed in an N type epitaxial layer 11 on an N type substrate 10 surrounding an element region. A P-type base layer 12 is formed by using a gate oxide film 20 and a polycrystalline Si gate electrode 21 as a mask and suitable apertures are drilled in an SiO2 film 13 to form an N type source layer 22 and an N contact layer 17. An electrode 14 which is contacted with the N type source layer 22 and electrodes 23 and 18 which are contacted with the protection rings 16 and the N layer 17 are provided and a high resistance amorphous Si layer 19, contacted with the electrodes 18, is formed on the SiO2 film 13 between the final step protection ring and the N type layer 17. A drain electrode 15 made of V-Ni-Au is applied to the back plane of the substrate. With this constitution, the expansion of the depletion layer in the Si substrate is enlarged and the electric field concentration is avoided by giving a potential gradient to the high resistance layer 19 so that a small size high dielectric strength planar type semiconductor device can be obtained.

37. 发明专利

JP2003092414A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003092414A
公开(公告)日：2003-03-28
申请号：JP2001281363
申请日：2001-09-17
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： WATANABE KIMINORI , ITOI TAKAO , KOYANAGI TAKESHI
IPC分类号： H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a lateral diode in which operation of a parasitic transistor is restrained while a high withstand voltage is ensured. SOLUTION: The lateral diode is provided with a first conductivity type cathode region (23) and an anode region (21) which are selectively formed on the surface of a semiconductor layer (19), and a first conductivity type RESURF region (25) which is formed overlapping with a peripheral part of the cathode region excepting the vicinity of the central part. Under the cathode region, a second conductivity type semiconductor region (19) is formed below which a first conductivity type buried layer (13) is formed. As a result, the parasitic transistor operation which is to be generated just below the cathode region can be effectively restrained.

38. 发明专利

JP2002026314A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002026314A
公开(公告)日：2002-01-25
申请号：JP2000205070
申请日：2000-07-06
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of improved breakdown strength. SOLUTION: Inside a device, a drain region 15 and source region 16 are enclosed with a p-well layer 14. A high-concentration n-type deep diffusion layer 19 is formed from the surface of a substrate 11 at a drain as deep as an embedded layer 12. The distance X between a drain contact region 20 and a source region 16 is larger than the film thickness Y of an epitaxial layer 13 on the embedded layer 12, with the length not preventing micronizing of an element.

39. 发明专利

JPH0715007A CONDUCTIVITY-MODULATION MOSFET 失效
公开(公告)号：JPH0715007A
公开(公告)日：1995-01-17
申请号：JP10864194
申请日：1994-05-23
申请人： TOSHIBA CORP
发明人： NAKAGAWA AKIO , YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI , OHASHI HIROMICHI
IPC分类号： H01L29/78 , H01L29/739
摘要： PURPOSE:To provide a conductivity-modulation MOSFET wherein latchup scarcely occurs. CONSTITUTION:In a conductivity-modulation MOSFET wherein p-type base diffusion layers 13 are formed in an n type high resistance layer 12 of a wafer having a p type drain layer 11 and the n type high resistance layer 12, an n type source diffusion layer is formed in the p-type base diffusion layer 13, a gate insulating film 16 and a gate electrode are formed on the base diffusion layers 13 turning to a channel region, and source electrodes 18 which are in contact with both of the diffusion layers 13 are formed, the gate electrode consists of a polycrystalline silicon film gate electrode 17 arranged so as to cover the n type high resistance layer 12 and an Al gate electrode 20 stacked on the electrode 17, and a p type base diffusion layer 15 is formed under the Al gate electrode 20.

40. 发明专利

JPH06342903A LATERAL CONDUCTIVITY MODULATION MOSFET 失效
公开(公告)号：JPH06342903A
公开(公告)日：1994-12-13
申请号：JP10864094
申请日：1994-05-23
申请人： TOSHIBA CORP
发明人： NAKAGAWA AKIO , YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI , OHASHI HIROMICHI
IPC分类号： H01L29/78 , H01L29/784
摘要： PURPOSE:To obtain a lateral conductivity modulation MOSFET, in which a latch-up is difficult to be generated. CONSTITUTION:A p-type base diffusion layer 33 is formed to a high resistance layer 32 section on the drain layer side of a semiconductor substrate wafer with an n- type high resistance layer 32 and a p type drain layer 40 selectively formed onto the surface of the layer 32, and an n'' type source diffusion layer 34 is formed into the base diffusion layer 33. In a lateral type conductivity modulation type MOSFET, a gate electrode 36 is shaped onto a the base diffusion layer 33 as a channel region held by the source diffusion layer 34 and the high resistance layer 32 through a gate insulating film 35, and a source electrode 37 brought into contact with both the source diffusion layer 34 and the base diffusion layer 33 is formed. An opening section exposed onto the wafer surface of the high resistance layer 32 is formed in an insular shape completely surrounded by the base diffusion layer 33, and the drain layer 40 is shaped selectively to the surface of a p type diffusion layer 39 formed on the surface of the high resistance layer 32.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式