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31. 发明专利

JPH05109813A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05109813A
公开(公告)日：1993-04-30
申请号：JP29986891
申请日：1991-10-19
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/321 , H01L23/485 , H01L23/52
摘要： PURPOSE:To obtain a semiconductor device with an electrode pad which permits high integration and has higher mechanical strength. CONSTITUTION:An electrode pad 1 is formed in an upper layer wiring, and a plurality of lower layer wirings 3, 5 and 6, including dummy wiring, are formed directly under the electrode pad 1. The electrode pad 1 is connected with these lower layer wirings 3 and 6, excluding a wiring 5 with a different electric potential, through a plurality of through holes 7. This enlarges the area of contact of a layer insulating film 12 with the electrode pad 1 and the lower layer wirings, and improves the mechanical strength of the device.

32. 发明专利

JPH04348526A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04348526A
公开(公告)日：1992-12-03
申请号：JP12062291
申请日：1991-05-27
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/3205 , H01L21/31 , H01L21/768 , H01L23/522
摘要： PURPOSE:To realize a flattened multi-layer interconnection, by eliminating unevenness on the surface of an interlayer insulating film, which is caused by roughness and fineness of a lower interconnection. CONSTITUTION:An oxide silicon film 9 is formed on Ti and Au layers 7 and 8, which are provided as power supply layers for electroplating. A lower interconnection 3 is formed with the oxide silicon film 9 patterned as a mask. Then, an insulating film having a simulated pattern corresponding to the isolation and connection of the power supply layers is formed by etching an oxide silicon film 9, an Au layer 8, and a Ti layer 7 selectively in sequence. Moreover, a silica film 5 is formed on the surface over these layers by a coating method so that the surface is made flat.

33. 发明专利

JPH04174541A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS MANUFACTURE 失效
公开(公告)号：JPH04174541A
公开(公告)日：1992-06-22
申请号：JP7926090
申请日：1990-03-28
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/768 , H01L21/31 , H01L23/522 , H01L23/532
摘要： PURPOSE:To improve flatness by selectively forming a first insulating film on lower layer wirings, covering the lower layer wiring side walls with a second insulating film, burying low permittivity material between the lower layer wirings, and connecting the lower layer wirings with the upper layer wiring via a through hole. CONSTITUTION:Lower layer wirings 102 are covered with a first insulating film 103 selectively formed on the lower layer wiring metal 102 on a semiconductor substrate 101, and a second insulating film 105 covering at least the side walls of the lower layer wirings 102. The region where the lower layer wirings do not exist is filled with a film 106 formed by spreading material whose relative permittivity is 2-3. A third insulating film 107 is formed on the whole part of the substrate 101 so as to cover the upper surfaces of the film 106 and the film 103, and sealing is performed. The wiring 102 is electrically connected with the upper layer wiring 109 via a through hole 108 formed in the film 107. By this structure, the low permittivity material formed by a spreading method or the like does not directly come into contact with the wiring. Since the low permittivity material is buried, superior flatness can be obtained.

34. 发明专利

JPH03196662A INTERCONNECTION STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS MANUFACTURE 失效
公开(公告)号：JPH03196662A
公开(公告)日：1991-08-28
申请号：JP33960289
申请日：1989-12-26
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/768 , H01L23/482 , H01L23/522
摘要： PURPOSE:To reduce an interconnection mutual capacity by a method wherein, after a multilayer interconnection is formed, one part of an interlayer insulating film sandwiched between interconnections on the same layer is removed by making use of interconnection metals of individual layers as a mask, a thin surface-protective film is formed and an air gap is formed. CONSTITUTION:A lower-layer interconnection 3 is formed on the surface of a semiconductor substrate 1 where a semiconductor element is formed; an upper-layer interconnection 6 is formed via a through hole 5; an interlayer insulating film 4 and a field insulating film 2 are etched partially by making use of the upper-part interconnection 6 and the lower-part interconnection 3 as a mask. Then, a sidewall insulating film 7 composed of the interlayer insulating film 4 is formed in a part which is situated at an end part of the lower-layer interconnection 3 and which is not covered with the upper-part interconnection. Then, when a thin surface-protective film 8 is formed, a complicated side face can be covered completely with the surface-protective film 8, and the sidewall insulating film 7 formed at the lower-layer interconnection 3 reinforces the surface-protective film 8. That is to say, the lower-layer interconnection 3 is insulated mutually by the sidewall insulating film 7, the surface protective film 8 and an air gap 9. Thereby, an interconnection mutual capacity can be reduced.

35. 发明专利

JPH02172261A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02172261A
公开(公告)日：1990-07-03
申请号：JP32650488
申请日：1988-12-25
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L21/768 , H01L23/528
摘要： PURPOSE:To prevent the corrosion of wiring by forming a punched-out pattern of a lower wiring in the vicinity of a part where a through hole on a wide lower wiring is to be formed, and forming an insulating film in a part of an interlayer insulating film by spin coating method. CONSTITUTION:A punched-out pattern 103 of a lower wiring is formed around a part, on a wide lower wiring 102, in which a through hole 107 is to be formed. Then an interlayer insulating film composed of the following is formed so as to cover the lower wiring 102; a first CVD insulating film 104, a coat formation insulating film 105 by spin coating method, and a second CVD insulating film 106. After the through hole 107 is formed in the interlayer insulating film, an upper layer 108 connecting with the lower wiring 102 via the through hole 107 is formed. As a result, the coat formation insulating film 105 is not exposed in the through hole aperture 107 even at a wide part of the lower layer wiring 102, and out gas does not generate from said film at the time of sputtering and heating in the later process. Thereby the corrosion of wiring can be prevented.

36. 发明专利

JPH02113554A WIRING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH02113554A
公开(公告)日：1990-04-25
申请号：JP26656288
申请日：1988-10-22
申请人： NEC CORP
发明人： MIZUSHIMA KAZUYUKI
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To reduce a capacitance generating between a wiring and a semiconductor substrate without increasing the thickness of an oxide film by constituting a part of the oxide film for element isolation by using a thick insulating film, and forming a part of wiring on the insulating film. CONSTITUTION:A part of an oxide film 13 for element isolation formed on a semiconductor substrate 11 is constituted by using a thick insulating film 14, and at least a part of a wiring 16 formed on the oxide film 13 is formed on the insulating film 14. That is, it is not necessary for all wiring to be formed on the thick insulating film 14, and only the wiring whose parasitic capacitance becomes a serious problem is formed thereon. By this set-up, the capacitance between the semiconductor substrate 11, the first wiring 16 and a second wiring 18 scarcely changes, when the thickness of the oxide film between the semiconductor substrate and the wiring is changed. Only the capacitance of large value between the first wiring and the semiconductor substrate decreases remarkably, so that the parasitic capacitance can be reduced without reducing the surface area of the first wiring 16. Thereby, a thick insulating film can be formed without affecting miniaturization, and the reduction of parasitic capacitance is enabled.

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