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31. 发明专利

JPS56169295A ERROR RETRIEVAL SYSTEM OF INFORMATION PROCESSOR 失效
公开(公告)号：JPS56169295A
公开(公告)日：1981-12-25
申请号：JP7224680
申请日：1980-05-30
申请人： FUJITSU LTD
发明人： NOJIMA KENICHI , TSUNODA HARUHIKO
IPC分类号： G06F12/16 , G06F11/00 , G06F12/08
摘要： PURPOSE:To secure the error retrieval of a main memory through simple constitution, by storing an error detection signal in a storage bit of an address array and by specifying corresponding information to be moved out. CONSTITUTION:If an error from information moved in from a main memory 2 is detected by the error correcting circuit 5 of an information processor 1, an error detection signal is applied to the storage bit S of an address array 4 via an OR circuit 6 applied with a storage indication. Consequently, information, wherein the error occurs, from the memory 2 is corrected as an object to be moved out without reference to the generation of the storage indication to write the corrected information in a buffer memory 3, and consequently the error of the main memory is retrieved with simple constitution, thereby improving the reliability of the information processor.

32. 发明专利

JPS54163644A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS54163644A
公开(公告)日：1979-12-26
申请号：JP7263978
申请日：1978-06-15
申请人： FUJITSU LTD
发明人： TSUNODA HARUHIKO
IPC分类号： G06F11/22 , G06F11/00 , G06F11/34

33. 发明专利

JPH0991344A CONTENT SALE PERIOD VERIFICATION SYSTEM AND CONTENT DECIPHERING KEY EXPIRATION DATE VERIFICATION SYSTEM 失效
公开(公告)号：JPH0991344A
公开(公告)日：1997-04-04
申请号：JP24212595
申请日：1995-09-20
申请人： FUJITSU LTD
发明人： YOSHIOKA MAKOTO , TSUNODA HARUHIKO , HASEGAWA KAZUHARU , AOE HIDESHI
IPC分类号： G06F12/14 , G06F21/00 , G06F21/10 , G06F21/62 , G06Q10/00 , G06Q20/00 , G06Q20/12 , G06Q30/06 , G06Q50/00 , G06Q50/10 , G11B20/10 , G06F17/60 , G06F15/00
摘要： PROBLEM TO BE SOLVED: To provide the content sale period verification system which can set the sale period of contents. SOLUTION: On a CD-ROM 11, the CD-ROM expiration date of this CD-ROM 11 and the content expiration date of the contents stored on the CD-ROM 11 are recorded. A CD-ROM (content) expiration date judgement part 13 of a personal computer 6 reads those expiration date and compares them with the machine data generated by a machine date generation part 17 and enables a purchase slip to be sent from a purchase slip transmission part 15 only when the machine date is in the expiration date. A CD-ROM (content) expiration date judgement part 31 of a center 1, on the other hand, compares the current date with a CD-ROM expiration date and a content expiration date registered in an article master 32k, and reads a key out of the article master and sends it to the personal computer 6 only when the CD-ROM number and content ID written into a received purchase slip are both in the expiration date.

34. 发明专利

JPH0364894B2 失效
公开(公告)号：JPH0364894B2
公开(公告)日：1991-10-08
申请号：JP18115584
申请日：1984-08-30
申请人： FUJITSU LTD
发明人： TSUNODA HARUHIKO
IPC分类号： G06F13/38 , G06F11/00 , G06F13/00 , G06F13/40

35. 发明专利

JPS59221056A CIRCUIT CONTROL METHOD 失效
公开(公告)号：JPS59221056A
公开(公告)日：1984-12-12
申请号：JP9526383
申请日：1983-05-30
申请人： FUJITSU LTD
发明人： TANABE KOUICHI , OGATA TETSUYA , TSUNODA HARUHIKO
IPC分类号： H04L1/22 , G06F13/00 , H04L13/00 , H04L13/10 , H04L29/02
摘要： PURPOSE:To prevent the transmission of wrong data despite a fault of a serial/ parallel converting circuit by using a pair of said converting circuits, combining a shift register with each converting circuit, and attaining switching both circuits with each other. CONSTITUTION:When a read command mode, the read data is fed to a main serial/parallel converting circuit 11 via a read data bus 3 and turned into the parallel data. This parallel data is set to a main reception shift register 13. At the same time, the read data is set to a slave reception shift register 14. In this case an error detection switch indicating circuit 20 is actuated when an error due to a fault of the circuit 11 is detected. Thus the read data is sent to a read data channel 5 from the register 14. The read data is fed to a slave serial/ parallel converting circuit 12 through the bus 3 after detection of the error and converted into the parallel data to be set to the register 14. Then the faulty circuit 11 is separated from a receiving circuit.

36. 发明专利

JPS59132028A Memory access control system 失效
标题翻译：存储器访问控制系统
公开(公告)号：JPS59132028A
公开(公告)日：1984-07-30
申请号：JP645683
申请日：1983-01-18
申请人： Fujitsu Ltd
发明人： MATSUZAKI SHIGEHARU , TSUNODA HARUHIKO
IPC分类号： G06F13/12 , G06F3/00 , G06F12/00
CPC分类号： G06F3/00
摘要： PURPOSE:To give a memory access right to the highest request level when memory access requests are generated simultaneously in plural request levels and to give the memory access right with a table logic when plural access requests are generated in the same level. CONSTITUTION:Request levels from channels 11, 12, 13, and 14 are decoded by decoding circuits 15, 16, 17, and 18. The hightest request level (0) of each of channels 11-14 is inputted to a multiplexer 23 and an OR circuit 19. The second highest request level (1) of each of channels 11-14 is inputted to a multiplexer 24 and an OR circuit 20, and the third hightest request level (2) is inputted to a multiplexer 25 and an OR circuit 21. The output of the OR circuit 19 is selected preferentially from outputs of OR circuits 19, 20, and 21 by a priority selecting circuit 29 and is sent to a multiplexer 30. The multiplexer 30 transmits the channel number, which acquires the memory access right, from a terminal C.
摘要翻译：目的：当在多个请求级别中同时生成存储器访问请求时，给予最高请求级别的存储器访问，并且在同一级别生成多个访问请求时，使用表逻辑给存储器访问权限。构成：通道11,12,13和14的请求电平由解码电路15,16,17和18解码。每个通道11-14的最高请求电平（0）被输入到多路复用器23和或电路19.每个通道11-14的第二最高请求电平（1）被输入到多路复用器24和“或”电路20，并且第三最高请求电平（2）被输入到多路复用器25和“或”电路 OR电路19的输出优先地由优先选择电路29的OR电路19,20和21的输出选择并被发送到多路复用器30.多路复用器30发送获取存储器访问的通道号对，从终端C.

37. 发明专利

JPS59105151A Controlling method of interruption 失效
标题翻译：中断控制方法
公开(公告)号：JPS59105151A
公开(公告)日：1984-06-18
申请号：JP21417182
申请日：1982-12-07
申请人： Fujitsu Ltd
发明人： OOKAWA MASAYUKI , TSUNODA HARUHIKO
IPC分类号： G06F13/24 , G06F9/48
CPC分类号： G06F9/4812
摘要： PURPOSE:To reduce hardware and to form a very large scale integrated circuit (VLSI) by collating an interruption priority test code by a microprogram with an output of an interruption factor holding circuit to detect the interruption factor and determine the priority. CONSTITUTION:A microprogram part 5 sends a test code to a register 6 from a factor with higher priority in accordance with the priority of each interruption factor previously fixed in each architecture. The test code inputted from the register 6 to the VLSI 8 is decoded by a decoder 9 and the decoded signal is collated with an interruption factor from a register 11. A coincident interruption factor is added to the address from the register 6 by an adder 7 and the interruption code in the microprogram part 5 is read out and sent to a memory 12.
摘要翻译：目的：通过将中断优先级测试代码与中断因子保持电路的输出结合起来，以便检测中断因素并确定优先级，来减少硬件并形成一个非常大规模的集成电路（VLSI）。构成：微程序部分5根据先前在每个架构中确定的每个中断因子的优先级，从具有较高优先级的因子向寄存器6发送测试代码。从寄存器6输入到VLSI 8的测试码由解码器9解码，解码信号与来自寄存器11的中断因数进行比较。通过加法器7将一致的中断因子从寄存器6加到地址并且读出微程序部分5中的中断代码并将其发送到存储器12。

38. 发明专利

JPS5858658A INSTRUCTION RETRY PROCESSING SYSTEM 失效
公开(公告)号：JPS5858658A
公开(公告)日：1983-04-07
申请号：JP15643981
申请日：1981-09-30
申请人： FUJITSU LTD
发明人： MATSUZAKI SHIGEHARU , TSUNODA HARUHIKO
IPC分类号： G06F11/14
摘要： PURPOSE:To retry an instruction even in case of an instruction of plural processing flows, by converting the instruction to a dummy and executing it before an suppressed processing flow, and normally executing the instruction after the suppressed processing flow, when retrying the instruction. CONSTITUTION:An instruction retry controlling circuit 3 instructs to retry an instruction, to an instruction controlling circuit 1 through a signal line l34 by use of a result of detection of an instruction processing suppressing flow sent from a signal line l2. When retrying an instruction of plural processing flows, the instruction retry controlling circuit 3 executes the instruction in a state that write to a register and store in a memory by the suppressed instruction, until the processing flow immediately before the suppressed processing, and after the flow by which the suppressed processing, the instruction controlling circuit 1 is set to a state that the instruction can be executed normally, and the remaining part of the instruction is executed, by which the instruction of plural processing flows is retried. When retrying the instruction, a data of a save register circuit 4 is read out as an operand address.

39. 发明专利

JPS589275A BUFFER CONTROLLING METHOD 失效
公开(公告)号：JPS589275A
公开(公告)日：1983-01-19
申请号：JP10778181
申请日：1981-07-10
申请人： FUJITSU LTD
发明人： TSUNODA HARUHIKO , NOJIMA KENICHI , MATSUZAKI SHIGEHARU
IPC分类号： G06F12/08 , G06F12/02
摘要： PURPOSE:To eliminate waiting of main storage operation by making operation so that when all blocks of n-column corresponding to mi-row are invalidated, all blocks of n-column corresponding to mi+1 row are invalidated. CONSTITUTION:The contents of a stop address register are made number of sets + L (length of a line), and inputted to an input terminal of a comparator 8. On the other hand, the contents of an effective address register 1 are made all ''0''. The prefetch baud 10 inputs address to an adder 11 which is at input of the address register 1. When there is carry from the line address, page address is increased by 1. By this, set position that becomes an object of operation is sent out to a set register 12 and an object set is designated to address array 3 and a buffer 6 by a decoder circuit 4. When this operation is repeated for the number of stes + L, it is detected by a comparator 8 and buffer invalidation operation comes to an end. Thus, waiting of main storage operation can be eliminated.

40. 发明专利

JPS5733471A Memory access control system for multiprocessor 失效
标题翻译：用于多处理器的存储器访问控制系统
公开(公告)号：JPS5733471A
公开(公告)日：1982-02-23
申请号：JP10550380
申请日：1980-07-31
申请人： Fujitsu Ltd
发明人： TSUNODA HARUHIKO
IPC分类号： G06F12/08 , G06F9/46 , G06F9/52 , G06F15/16 , G06F15/177
CPC分类号： G06F9/52
摘要： PURPOSE:To reduce the mean access queuing time for the entire system, by locking only the block region to be originally locked and permitting the memory access request given from another CPU to another storage region. CONSTITUTION:The access address information for another CPU is set to another address register 8; the access address information for own CPU is set to own address register 9; and the lock information for the register 9 is set to a lock register 13 respectively. At the same time, the access request blocks for own CPU and another CPU are compared 11-0 and 11-1. Then the memory access requests given from the own CPU and another CPU have a conflict. And a memory access is inhibited for another CPU as long as the lock-indicated own access request block is idential to another access request block. Otherwise the memory access is permitted.
摘要翻译：目的：为了减少整个系统的平均访问排队时间，只通过锁定最初被锁定的块区域，并允许从另一个CPU给另一个存储区域的存储器访问请求。构成：另一个CPU的访问地址信息设置为另一个地址寄存器8; 自己的CPU的访问地址信息设置为自己的地址寄存器9; 并且用于寄存器9的锁定信息分别设置到锁定寄存器13。同时，将自己的CPU和另一个CPU的访问请求块比较为11-0和11-1。那么从自己的CPU和另一个CPU给出的内存访问请求有冲突。只要锁指示的自己的访问请求块与另一个访问请求块相同，则对另一个CPU禁止存储器访问。否则允许内存访问。

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