专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明专利

JPS63143654A ARBITER CIRCUIT 失效
公开(公告)号：JPS63143654A
公开(公告)日：1988-06-15
申请号：JP29072686
申请日：1986-12-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： MIHARA MASAAKI , KOBAYASHI TOSHIFUMI
IPC分类号： G06F13/362 , G06F13/14 , G06F13/26
摘要： PURPOSE:To execute a competition deciding processing without simultaneously activating input signals to an RS flip flop by providing the titled circuit with a device for controlling a transfer gate for transmitting a 2nd request signal by a 1st request signal. CONSTITUTION:When a request signal REQ-B is turned from 'L' to 'H', a connection terminal 4 is turned from 'L' to 'H' with the delay of time ta. A connection terminal 4d is also turned from 'H' to 'L' with the delay of time tb from the ta. Thereby, the voltage of a terminal 4e is kept at 'L' only for the time ta+tb from the time turning the request signal REQ-B from 'L' to 'H' and the transfer gate 5 is turned off. When a request signal REQ-A is turned from 'L' to 'H', the connection terminal 4a is turned from 'H' to 'L'. When the transfer gate 5 is ON, the connection terminal 4b is turned from 'L' to 'H' in accordance with the change of the connection terminal 4a, but when the gate 5 is OFF, the connection terminal 4b is held at the immediately preceding state by a latch circuit constituted of inverters 2c, 2d.

32. 发明专利

JPS6310397A INPUT CIRCUIT FOR DYNAMIC RANDOM ACCESS MEMORY 失效
公开(公告)号：JPS6310397A
公开(公告)日：1988-01-16
申请号：JP15650886
申请日：1986-07-01
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUMOTO NORIMASA , KOBAYASHI TOSHIFUMI
IPC分类号： G11C11/413 , G11C11/34 , G11C11/401 , G11C11/408 , G11C11/409
摘要： PURPOSE:To prevent an excessive abnormal current from being conducted in an internal circuit when its power source is applied by generating a pulse with width longer than time required for precharging the internal circuit and inhibiting the action of an input circuit until the pulse finished precharging the internal circuit. CONSTITUTION:Time covering a time T0 when the power source Vcc is led and a time T2 when an internal RAS signal is led at a level 'H' can be set longer than the time required for precharging the internal circuit at the time T0 by appropriately selecting a time constant decided by the resistance value R of a resistance 6 and the capacity C of a capacitor 8. Consequently, even if the power source Vcc of the internal circuit is applied with an external RAS signal at a level 'L', a POR signal with a prescribed width can maintain the internal RAS signal at the level 'L' at lest until the internal circuit is completely precharged. Thus an excessive abnormal current is never conducted in the internal circuit from the power source Vcc when said source Vcc is applied.

33. 发明专利

JPS6280897A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6280897A
公开(公告)日：1987-04-14
申请号：JP22210285
申请日：1985-10-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUMOTO NORIMASA , KOBAYASHI TOSHIFUMI , MASUKO KOICHIRO
IPC分类号： G11C11/401 , G11C11/406 , G11C11/4076 , G11C11/409 , G11C11/4091 , G11C11/4097
摘要： PURPOSE:To reduce the power at refreshing by not connecting a bit line at a side not selected at refreshing cycle to a sense amplifier in a semiconductor storage device of a shared sense amplifier system. CONSTITUTION:A signal phiREF goes to L at refreshing cycle, AND gates 13R, 13L are both closed and when the R-side memory cell or the like is selected, a selection signal AR goes to H and a signal AL goes to L and AND gates 14R, 14L are respectively opened and closed. Then outputs phi2R, phi2L of OR gates 16R, 16L go respectively to H, L in response to a clock phi, only the R-side bit line is connected to the sense amplifier via a transfer transistor and no charge current flows to the L-side bit line and the power consumption is halved.

34. 发明专利

JPS61148860A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61148860A
公开(公告)日：1986-07-07
申请号：JP27116584
申请日：1984-12-21
申请人： MITSUBISHI ELECTRIC CORP
发明人： MOROOKA KIICHI , YAMADA MICHIHIRO , KOBAYASHI TOSHIFUMI , MASUKO KOICHIRO
IPC分类号： H01L27/06 , H01L27/02
摘要： PURPOSE:To make it possible to ensure operational allowance, by providing a switch circuit, which controls the amount of current of a discharge circuit in correspondence with an operation control signal of a semiconductor integrated circuit device, in the discharge circuit between a substrate-potential and a reference-potential, thereby reducing the fluctuation of the substrate-potential due to the operation of the semiconductor integrated circuit device. CONSTITUTION:When an operation control signal has the same potential as that of a reference-potential wiring GND, a substrate-potential wiring VBB wiring is kept at a level, which is lower than the reference-potential wiring GND by the sum of the threshold voltages of field effect transistors Q11-Q15. When the operation control signal is increased to a potential, which is sufficiently higher than the threshold voltage of the transistor 15, the transistor 15 becomes a conducting state. and its potential is increased to the potentials of the gate and drain of the transistor Q14 and the reference-potential wiring GND. The current supplying capability of a discharge circuit 1 becomes large. Even if the semiconductor integrated circuit device is operated and the substrate- potential is decreased, the specified potential can be immediately restored and kept constant.

35. 发明专利

JPS6149456A Mos type semiconductor integrated circuit 失效
标题翻译： MOS型半导体集成电路
公开(公告)号：JPS6149456A
公开(公告)日：1986-03-11
申请号：JP17200284
申请日：1984-08-17
申请人： Mitsubishi Electric Corp
发明人： KOBAYASHI TOSHIFUMI , YAMADA MICHIHIRO , MASUKO KOICHIRO , MIYAMOTO HIROSHI , ARIMOTO KAZUTAMI , MOROOKA KIICHI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02
CPC分类号： H01L27/0218
摘要： PURPOSE:To prevent a change into a positive value of substrate voltage by forming a MOSFET for clamping substrate voltage in which a drain and a gate are connected to a substrate and a source is connected to a ground. CONSTITUTION:A bonding pad 3 is connected to a die frame for a package with which a chip 1 for a MOS dynamic RAM is die-bonded, and substrate voltage is applied to a substrate for the chip 1. When a memory cell is formed generally by using a process of double layer poly Si, a memory cell plate is constituted by first poly Si, but a gate oxide film in first poly Si is thinned extremely. A grounding wiring 4 and an output 5 from a substrate-voltage generating circuit are wired so as to make a round on the outer circumference of the chip 1. Accordingly, when a first poly Si gate FET in which a drain and a gate are connected to the wiring 5 in a transistor region 8 for clamping substrate voltage and a source is connected to the wiring 4 is formed, a MOSFET for clamping substrate voltage having extremely low threshold voltage can be constituted.
摘要翻译：目的：通过形成用于钳位衬底电压的MOSFET来防止衬底电压的正值变化，其中漏极和栅极连接到衬底并且源极连接到地。构成：接合焊盘3连接到用于MOS动态RAM的芯片1裸片结合的封装的管芯框架，并且将衬底电压施加到用于芯片1的衬底。当通常形成存储器单元时通过使用双层多晶硅的工艺，存储单元板由第一多晶硅构成，但第一多晶硅中的栅极氧化膜极其稀薄。来自基板电压产生电路的接地布线4和输出5被布线以在芯片1的外圆周上圆形化。因此，当连接漏极和栅极的第一多晶硅栅极FET 对于用于钳位基板电压的晶体管区域8中的布线5，并且形成与布线4连接的源极，可以构成用于钳位具有极低阈值电压的基板电压的MOSFET。

36. 发明专利

JPS6120298A Dymanic random access memory 失效
标题翻译： DYMANIC随机存取存储器
公开(公告)号：JPS6120298A
公开(公告)日：1986-01-29
申请号：JP14079284
申请日：1984-07-05
申请人： Mitsubishi Electric Corp
发明人： MIYAMOTO HIROSHI , YAMADA MICHIHIRO , MASUKO KOUICHIROU , KOBAYASHI TOSHIFUMI , ARIMOTO KAZUTAMI , MOROOKA KIICHI
IPC分类号： G11C11/407 , G11C11/34 , G11C11/401 , G11C11/408
摘要： PURPOSE: To obtain a dynamic RAM advantageous in layout chip area and in which penetration radio wave from power source potential to grounding potential in a column predecoder does not flow by making decoder operation in the column predecoder only by a signal corresponding to a column address.
CONSTITUTION: Sense amplifiers SA are arranged at the center of each block, and divided column decoders CD1 and CD2 are arranged on both sides of the sense amplifiers and memory cells MC are arranged further outside. A row decoder RD is placed on upper end of all blocks. PD1WPD4 are column predecoders, and signals CA1 or C'A'1, CA2 or C'A'2 corresponding to 2 bits of the column address and a column address driving signal CY are connected to each column predecoder. CY1WCY4 are column predecoded signals.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了获得有利于布局芯片面积的动态RAM，并且在列预解码器中，从源电位到接地电位的穿透无线电波不能仅通过与列地址对应的信号在列预解码器中进行解码器运行。构成：感测放大器SA布置在每个块的中心，并且分离列解码器CD1和CD2被布置在读出放大器的两侧，并且存储单元MC被进一步布置在外部。行解码器RD放置在所有块的上端。 PD1-PD4是列预解码器，并且对应于列地址的2位和列地址驱动信号CY的信号CA1或C'A'1，CA2或C'A'2连接到每列预解码器。 CY1-CY4是列预编码信号。

37. 发明专利

JPS60261099A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS60261099A
公开(公告)日：1985-12-24
申请号：JP11775384
申请日：1984-06-07
申请人： MITSUBISHI ELECTRIC CORP
发明人： KOBAYASHI TOSHIFUMI , YAMADA MICHIHIRO , MASUKO KOUICHIROU , MIYAMOTO HIROSHI , ARIMOTO KAZUTAMI , MOROOKA KIICHI
IPC分类号： G11C11/404 , G11C11/34 , G11C11/401
摘要： PURPOSE:To prevent destruction of element without lowering read margin while preventing the floating of the semiconductor substrate voltage at application of power by connecting an MOS transistor (TR) between a memory cell of one TR and one capacitor type and a power supply so as to attain high voltage drive at a value over a threshold value. CONSTITUTION:An MOS TRT1 is connected between the power supply 8 and a plate of a memory cell. A high voltage is impressed from a high voltage generating circuit 9 comprising a charge pump circuit and a clamp circuit to a gate of the TRT1 at application of power via a capacitor C2 and a node N1 connected thereto, and when the level of the node N1 reaches the steady-state being a threshold voltage or over, the TRT1 is turned on. Thus, the voltage rise after applciation of power is slow, the floating of the semiconductor substrate voltage in capacitance coupling with the memory cell plate is prevented and when the on-resistance of the TRT1 is decreased, the read margin reduction in the memory cell due to the voltage change of the memory plate is avoided, and no excess current flows to TRs around the memory cell and destruction of the element is prevented.

38. 发明专利

JPS60211864A Input circuit for semiconductor device 失效
标题翻译：半导体器件的输入电路
公开(公告)号：JPS60211864A
公开(公告)日：1985-10-24
申请号：JP6942184
申请日：1984-04-05
申请人： Mitsubishi Electric Corp
发明人： YAMAGATA NARIHITO , YAMADA MICHIHIRO , MIYAMOTO HIROSHI , MOROOKA KIICHI , ARIMOTO KAZUTAMI , KOBAYASHI TOSHIFUMI , MASUKO KOUICHIROU
IPC分类号： H01L29/41 , H01L23/485
CPC分类号： H01L24/05 , H01L23/485 , H01L2224/05554 , H01L2924/00014 , H01L2924/01013 , H01L2924/01082 , H01L2224/05599
摘要： PURPOSE:To prevent breakdown due to an electrostatic surge in a connecting section between a first diffusion layer and a second diffusion layer gy gently connecting said first diffusion layer and second diffusion layer by the connecting section, width thereof slowly changes. CONSTITUTION:Currents from a bonding pad reach to a first diffusion layer 4a thrugh an aluminum lead wire 1 and a polysilicon layer 2. The currents flow into a second diffusion layer 4b having width narrower than the first diffusion layer 4a from the first diffusion layer 4a, but the sudden concentration of currents to a connecting section between the first diffusion layer 4a and the second diffusion layer 4b can be avoided because the width of the connecting section between both layers 4a and 4b gradually reduceds at that time. Accordingly, breakdown due to an electrostatic surge in the connecting section 4c between the first diffusion layer 4a and the second diffusion layer 4b can be prevented.
摘要翻译：目的：为了防止由连接部分轻轻地连接所述第一扩散层和第二扩散层的第一扩散层和第二扩散层之间的连接部分中的静电浪涌导致的破坏，其宽度缓慢变化。构成：来自焊盘的电流到达第一扩散层4a，而铝导线1和多晶硅层2.电流从第一扩散层4a流入具有比第一扩散层4a窄的宽度的第二扩散层4b 但是由于两层4a和4b之间的连接部分的宽度在此时逐渐减小，所以可以避免对第一扩散层4a和第二扩散层4b之间的连接部分的电流的突然浓度。因此，可以防止由于第一扩散层4a和第二扩散层4b之间的连接部分4c中的静电浪涌引起的故障。

39. 发明专利

JPS60171697A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS60171697A
公开(公告)日：1985-09-05
申请号：JP2889384
申请日：1984-02-15
申请人： MITSUBISHI ELECTRIC CORP
发明人： MIYAMOTO HIROSHI , MOROOKA KIICHI , ARIMOTO KAZUTAMI , MASUKO KOUICHIROU , YAMADA MICHIHIRO , KOBAYASHI TOSHIFUMI
IPC分类号： G11C11/401 , G11C11/34 , G11C11/409 , G11C11/41
摘要： PURPOSE:To access at a high speed by providing a bus line at every plural blocks and connecting the bus line of a block selected by a column address to the data line connected to a preamplifier. CONSTITUTION:When a selecting line CL11, etc., in column address lines CL11- CL1m are selected by a column decodeer CD1, FETQ11a and Q11b are on and bus lines BL11 and BU1 of a bit line and its block B1 are connected to an anti BL11 and an anti BU1. The BU1 and the anti BU1 are connected to a preamplifier PA through a data line DL and an anti DL. Only a bus line of the selected block is connected to a data line connected to a preamplifier, a load capacity is reduced, and the preamplifier operates at a high speed. As a result, a semiconductor memory device can be accessed at a high speed.

40. 发明专利

JPS6050694A DYNAMIC RANDOM ACCESS MEMORY 失效
公开(公告)号：JPS6050694A
公开(公告)日：1985-03-20
申请号：JP15670183
申请日：1983-08-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： MASUKO KOUICHIROU , YAMADA MICHIHIRO , ARIMOTO KAZUTAMI , MIYAMOTO HIROSHI , KOBAYASHI TOSHIFUMI , MOROOKA KIICHI
IPC分类号： G11C11/407 , G11C7/06 , G11C7/10 , G11C11/4091 , G11C11/34
摘要： PURPOSE:To constitute a titled memory so that a level of an output data does not drop even at a hidden refresh time by providing a transistor in which an output driving signal is impressed to the gate, between the gate of an output stage driver transistor of an output driving signal generating circuit and a ground. CONSTITUTION:The potential of nodes N1, N3 is latched by an output stage driver transistor (TR) Q2 of an output driving signal generating circuit DVR, and a TRQ4 in which an output driving signal is impressed to the gate, between the gate of said TRQ2 and a ground. While the node N3 is in a high level, the TRQ4 is turned on, the node N1 is latched by the ground potential, the potential is not raised even by coupling of a noise voltage, etc., the TRQ2 continues an off-state, and the node N3 holds a high level. Accordingly, as for a dynamic RAM, a level of an output data does not drop even at a hidden refresh time, through a main amplifier MA driven by the circuit DVR.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式