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    • 32. 发明专利
    • MANUFACTURE OF ELECTRONIC CIRCUIT SUBSTRATE
    • JPS6451693A
    • 1989-02-27
    • JP20961187
    • 1987-08-24
    • MATSUSHITA ELECTRIC IND CO LTD
    • NAKAMURA HISASHIHARUTA YOICHINISHIDA KOJIKAWAYAMA MASARU
    • H05K3/32H05K1/09H05K3/24H05K3/34
    • PURPOSE:To reduce the connection resistance inbetween circuit elements and a circuit conductor layer, and to improve the reliability of connection, by a method wherein small-sized circuit elements of plane connection type are mounted before conductive resin on which a circuit conductor layer is formed by screen printing method is not cured, and then an electronic circuit is constituted by depositing simultaneously a conducting metal layer on both a conductive resin layer fixed by an electroless plating and an external connection terminal layer for circuit elements. CONSTITUTION:On the main surface of an insulating substrate 5, paste composed of conductive resin 6 obtained by electroless plating is spread in a desired form of wiring circuit pattern, by screen printing art. Then, small-sized circuit elements 7 are mounted. External connection terminals 8, 8' of the circuit elements 7 are brought into contact with a part of conductive resin 6 in the uncured state, and then the conductive resin 6 is cured. One in which the small-sized circuit elements 7 are fixed at specified positions of an insulating substrate 5 with the conductive resin 6, is dipped in the electroless plating solution, and a conducting metal layer 9 is deposited on the surface of the conductive resin 6 fixed in the form of a wiring circuit, and on the external connection terminals 8, 8' of the circuit element 7.
    • 33. 发明专利
    • HYBRID INTEGRATED CHIP MODULE
    • JPS63226053A
    • 1988-09-20
    • JP5935887
    • 1987-03-13
    • MATSUSHITA ELECTRIC IND CO LTD
    • NISHIDA KOJI
    • H01L23/538H01L23/32H01L23/52H05K3/46
    • PURPOSE:To facilitate a printing process and prevent a substrate edge electrode section from degrading in conductivity by a method wherein a plurality of internal leadout electrodes are provided along the bottom circumference of a substrate mounted with a wiring circuit and the substrate is placed on a chip carrier provided with a plurality of external leadout electrodes to be connected to said internal leadout electrodes. CONSTITUTION:A printed wiring circuit substrate 1 includes a single-layer or multilayer wiring circuit, and is provided with a plurality of internal leadout electrodes 3 along its bottom circumference for input/output signals. A glass- made protecting film 9 is provided. In a chip carrier 4, along the peripheral walls of a package, grooves 5 are provided, which correspond to the internal leadout electrodes 3. Along the circumference of the chip carrier 4, a plurality of solderable external leadout electrodes 6 are built at equal intervals. The internal leadout electrodes 3 of the printed wiring circuit substrate 1 to be installed thereon are soldered to said external leadout electrodes 6. Resin is caused to flow into an opening 8 provided at the middle of the chip carrier 4 for the protection of chip parts 7 against moisture. The resin also establishes adhesion between the printed wiring circuit substrate 1 and chip carrier 4.