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31. 发明专利

JPH1139216A SEMICONDUCTOR STORAGE AND CACHE MEMORY SYSTEM 失效
公开(公告)号：JPH1139216A
公开(公告)日：1999-02-12
申请号：JP19803397
申请日：1997-07-24
申请人： HITACHI LTD
发明人： YABUKI SHINOBU , USAMI MASAMI , SAITO KAYOKO , NAKAHARA SHIGERU , NISHIYAMA MASAHIKO
IPC分类号： G06F12/08
摘要： PROBLEM TO BE SOLVED: To optionally decide whether the highest priority should be given to improvement of the throughput of a cache memory or reduction of the power consumption by outputting the data on a designated way to the outside in a full access mode and then outputting the data on only a single way to the outside in a unique access mode. SOLUTION: The control means 4, 11, 14 and 15 control the memory operations to plural ways based on an ATYP (access type designation) signal and a WSEL (way selection) signal. That is, the means 4, 11, 14 and 15 instruct all ways A and B to output the data on both ways A and B selected by the WSEL signal after the memory cell selection performed based on an external address signal to the outside by means of the ATYP signal in a read operation mode. When a unique access is designated by the ATYP signal in the read operation mode, the memory cell selection of the way A or B is performed based on the external address signal and the data are outputted to the outside.

32. 发明专利

JPH10340586A SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSOR 失效
公开(公告)号：JPH10340586A
公开(公告)日：1998-12-22
申请号：JP14936397
申请日：1997-06-06
申请人： HITACHI LTD
发明人： NISHIYAMA MASAHIKO , YABUKI SHINOBU
IPC分类号： G11C11/413
摘要： PROBLEM TO BE SOLVED: To shorten a write cycle time and to improve the reliability of data. SOLUTION: A parity bit storage area for storing a parity bit is provided in each of plural memory mats 50, 60, 70, 80, parity bit generating circuits 51, 61, 71, 81 is provided for logically calculating the data written into the memory mats to generate the parity bit until a write address signal is distributed to the plural memory mats through the address distribution system and by generating the parity bit until the write address signal is distributed to the plural memory mats through the address distribution system, the reliability of dada is improved without affecting a data write cycle.

33. 发明专利

JPH10111832A MEMORY SYSTEM 失效
公开(公告)号：JPH10111832A
公开(公告)日：1998-04-28
申请号：JP26391896
申请日：1996-10-04
申请人： HITACHI LTD
发明人： YABUKI SHINOBU , NISHIYAMA MASAHIKO , NAKAHARA SHIGERU , USAMI MASAMI , SAITO KAYOKO
IPC分类号： G06F12/08
摘要： PROBLEM TO BE SOLVED: To realize low power consumption by reducing the times of access in a large scale memory and reducing the number of operations in a high power consumption output part inside the large scale memory. SOLUTION: This cache memory system having the cache memory of multi- way set associative correspondence is constituted of CPU, a tag memory 2 and a data memory, etc. Then, the tag memory 2 storing tag addresses for the portion of the number of ways is the secondary cache memory with the one-chip conversion of 8-way set associative correspondence and separatedly arranged into a large scal address memory 4 storing the tag addresses and a small scale of effective bit memory 5 storing only an effective bit corresponding to the tag addresses. The reading operatiton of the address memory 4 is stopped concerning the way where a result obtaianed by reading the effective bit memory 5 is invalid.

34. 发明专利

JPH1083672A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1083672A
公开(公告)日：1998-03-31
申请号：JP26128296
申请日：1996-09-10
申请人： HITACHI LTD
发明人： KAWAGUCHI ETSUKO , NISHIYAMA MASAHIKO
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a RAM in which word constitution can be changed in a standpoint of circuit. SOLUTION: A memory block consisting of a plurality of memory cells provided at plural word lines, plural data lines, and cross points of these word lines and data lines select one memory cell from each of plural memory blocks by an address selecting circuit for plural memory cell arrays, while validate the selecting operation by a first selecting signal for a first group of memory blocks being half of the plural memory blocks, validate the selecting operation by a second selecting signal for a second group of memory blocks being residual half of the plural memory blocks, the first selecting signal and the second selecting signal are formed with address signals indicating the first or the second memory blocks and a mode switching signal indicating validation/invalidation of an address signal, and memory access of word constitution of two kinds is switched by selecting the first or second group of memory blocks or the first and the second groups of memory blocks.

35. 发明专利

JPH07335762A DESIGN METHOD OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07335762A
公开(公告)日：1995-12-22
申请号：JP12540694
申请日：1994-06-07
申请人： HITACHI LTD
发明人： NISHIYAMA MASAHIKO , USAMI MASAMI , IWABUCHI MASATO
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52
摘要： PURPOSE:To improve the integration degree of an LSI while preventing a crosstalk generated between wirings by a simple method. CONSTITUTION:When a wiring pattern is designed, pitches (h) among wiring tracks H, H... used for designing the wiring pattern of an LSI are predetermined, wirings are divided into the specified wiring (L2), in which a timing design having high accuracy is required, and the wirings except the wiring (L2), the specified wiring L2 is laid out along the wiring track separated from the wiring tracks, on which other wirings are laid out, at two pitches, and other wirings (L1) are laid out mutually along the wiring tracks at one pitches. Accordingly, the dispersion of the delay time of specific signals (such as clock signals) is prevented, and the integration degree of the whole LSI can also be improved while obviating noises.

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