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31. 发明专利

JPH07161942A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH07161942A
公开(公告)日：1995-06-23
申请号：JP30291893
申请日：1993-12-02
申请人： SHIBATA SUNAO , OMI TADAHIRO
发明人： KOTANI KOJI , SHIBATA SUNAO , OMI TADAHIRO
IPC分类号： G06F15/18 , G06N3/063 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To improve the reliability of a neuron MOS transistor by adding a switch to a floating gate of neuron MOS transistor and by making charge remaining in the floating gate or injected escape rapidly through the switch. CONSTITUTION:One end of a switch 107 of neuron MOS transistors 101, 102 is connected to a specified signal line and excessive charge existing in a floating gate 103 can be removed by properly controlling the switch 107. Therefore, it is possible to prevent a threshold value of the neuron MOS transistor 103 from changing with time and to improve reliability of a neuron MOS integrated circuit. Furthermore, since threshold value change can be restrained low, the number of maximum allowable inputs of a neuron MOS transistor can be increased and a higher functional neuron MOS integrated circuit can be realized.

32. 发明专利

JPH06252744A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH06252744A
公开(公告)日：1994-09-09
申请号：JP5774893
申请日：1993-02-22
申请人： SHIBATA SUNAO , OMI TADAHIRO
发明人： SHIBATA SUNAO , KOTANI KOJI , OMI TADAHIRO
IPC分类号： G06F7/04 , G06G7/60 , G06N3/063 , H03K19/21
摘要： PURPOSE:To provide a semiconductor integrated circuit in which data matching is implemented at a high speed through the use of a simple circuit. CONSTITUTION:The semiconductor integrated circuit having at least one 1st input terminal 117 and at least one 2nd input terminal 115 receiving a voltage signal, and at least one output terminal 113 to provide a predetermined signal at the output terminal 113 when a difference of numerals expressed by two sets of signals inputted respectively to the 1st and 2nd input terminals 117, 115 is smaller than a predetermined value includes at least two inverters 124, 125 comprising neuron MOS transistors(TRs) 101, 103 and is characterized in that the two sets of signals or signals subject to predetermined processing partly are inputted to at least one of input gates of each inverter.

33. 发明专利

JPH06139380A SEMICONDUCTOR NEURAL CIRCUIT DEVICE 失效
公开(公告)号：JPH06139380A
公开(公告)日：1994-05-20
申请号：JP31413992
申请日：1992-10-29
申请人： SHIBATA SUNAO , OMI TADAHIRO
发明人： SHIBATA SUNAO , OMI TADAHIRO
IPC分类号： G06F15/18 , G06G7/60 , G06N3/063 , G06N99/00 , H01L21/822 , H01L27/04 , H01L29/78 , H01L29/784
摘要： PURPOSE:To provide a semiconductor neural circuit device which is capable of making a neural network learned effectively by a very simple circuit and has a self learning function. CONSTITUTION:This device has plural number of synapse circuits outputting weighted values and neuron circuits 101 determining the linear addition results of the output signals of the synapse circuits and outputting signal voltage of a high level and a low level for a prescribed threshold VTH. As for a learning in which a total value Z is made larger at the time of learning each neuron circuit 101, the weighted value of the prescribed synapse circuit which inputs a signal in a neuron circuit of epsilon is increased by a prescribed positive value only in the case of VTH-epsilon

34. 发明专利

JPH06125049A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH06125049A
公开(公告)日：1994-05-06
申请号：JP17029292
申请日：1992-06-03
申请人： SHIBATA SUNAO , OMI TADAHIRO
发明人： SHIBATA SUNAO , OMI TADAHIRO
IPC分类号： H01L21/8247 , G06N3/063 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To generate both a positive and negative weights with a single 5-V source without allowing any steady-state current to flow by respectively connecting the sources of a first and second MOS transistors to a third floating gate through a first and second capacitors. CONSTITUTION:The output signal Vi of a neuron of the preceding stage becomes VDD or 0 (zero) V depending upon the firing or non-firing of the neuron. A floating gate 101 is composed of the gate electrodes of an NMOS 102 and PMOS 103. Input gates Vx and Vy decide the potential at the gate 101. A write electrode VE delivers and receives electric charges. SiO2 is formed between the floating electrode and write electrode 107 and when the potential difference between both electrodes 101 and 107 becomes larger, an electric current starts to flow and the quantity of electric charges in the floating gate 101 changes. Output voltages V and V appearing at two output terminals 108 and 108' are coupled with the floating gate 110 of a neuron of the poststage through capacitors C1 and C2.

35. 发明专利

JPH0653431A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0653431A
公开(公告)日：1994-02-25
申请号：JP22216692
申请日：1992-07-29
申请人： SHIBATA SUNAO , OMI TADAHIRO
发明人： SHIBATA SUNAO , OMI TADAHIRO
IPC分类号： H01L27/10 , G06N3/063 , H01L27/115 , H01L29/788 , H03K5/24
摘要： PURPOSE:To allow high rate comparison of the size of a plurality of data by detecting variation of output voltage from an inverter circuit due to temporal variation of signal voltage and subjecting a specific inverter to positive feedback. CONSTITUTION:A common signal voltage is applied onto the first input gate 105 of an inverter circuit comprising neuron MOS transistors 101, 102. A predetermined second signal voltage is applied onto the second input gate 106 of the inverter circuit. Output voltage variation of the inverter circuit due to temporal variation of the first and/or the second signal voltage is detected and fed positively back to the inverter. This constitution allows high rate comparison of the size of a plurality of data.

36. 发明专利

JPH03165519A WASHING DEVICE 失效
公开(公告)号：JPH03165519A
公开(公告)日：1991-07-17
申请号：JP30562989
申请日：1989-11-24
申请人： OMI TADAHIRO
发明人： OMI TADAHIRO , SHIBATA SUNAO
IPC分类号： H01L21/304 , B05B7/28 , B05B7/30 , B05B7/32 , H01L21/00
摘要： PURPOSE:To make it possible to successively wash a large quantity of materials to be washed by mixed chemical solution without contamination by a method wherein a plurality of suction tubes, which are connected to a jet-stream tube at prescribed interval, and a plurality of chemical liquid vessels, in which the end opening of the suction tubes are inserted, are provided. CONSTITUTION:Two suction tubes 4a and 4b, which are communicated to a jet-stream tube 1 while being separated by a prescribed distance, are connected to the jet-stream tube 1, and the suction tubes are inserted to chemical solution vessels 5a and 56 respectively. When a pressure-feeding pump 2 is operated, the solution medium which is sucked up from a liquid refrigerant vessel 3 is allowed to flow in the jet-stream tube 1 along the longitudinal direction of the tube. At this time, the chemical liquid is sucked up from the chemical liquid vessels 5a and 5b by the jet stream of the solution medium, it is mixed with the solution medium of the jet-stream tube 1, and the mixture is jetted out from the end opening of the jet-stream tube 1. The material 6 to be washed is washed by the jetted mixture liquid. As a result, the material 6 to be washed can be washed by the chemical solution repeatedly without contamination, and also the washing device is protected from corrosion and the like.

37. 发明专利

JP2000323469A THIN FILM FORMING DEVICE AND METHOD 失效
公开(公告)号：JP2000323469A
公开(公告)日：2000-11-24
申请号：JP2000003025
申请日：2000-01-11
申请人： OMI TADAHIRO
发明人： OMI TADAHIRO , SHIBATA SUNAO , UMEDA MASARU
IPC分类号： C23C14/40 , H01L21/203 , H01L21/285 , H01L21/31
摘要： PROBLEM TO BE SOLVED: To provide a thin film forming device and a method, where a semiconductor substrate is less damaged by impact of ions, and a target sputtering rate can be accurately lessened or enhanced. SOLUTION: A thin film forming device has a structure where a first electrode and a second electrode are arranged confronting each other in a vacuum chamber, a first high-frequency power supply is connected to the first electrode, a second high-frequency power supply is connected to the second electrode, and the material of a target mounted on the second electrode is deposited on a substrate mounted on the first electrode by sputtering the target, where a first circuit which is resonant with only the output frequency of the second high-frequency power supply is connected to the first electrode, and a second circuit which is resonant with only the output frequency of the first high-frequency power supply is connected to the second electrode. RF power supplies 111a to 111d are connected to targets 109a to 109d through the intermediary of tuning circuits 110a to 110d, and RF power supplies 113a to 113d are connected to wafer holders 107a to 107d through the intermediary of tuning circuits 112a to 112d.

38. 发明专利

JPH11306268A SEMICONDUCTOR ARITHMETIC UNIT 失效
公开(公告)号：JPH11306268A
公开(公告)日：1999-11-05
申请号：JP12428798
申请日：1998-04-17
申请人： SHIBATA SUNAO , OMI TADAHIRO , ULTLA CLEAN TECHNOLOGY KAIHATS
发明人： SHIBATA SUNAO , OMI TADAHIRO , NAKADA AKIRA , MORIMOTO TATSURO , NITTA TAKEHISA
IPC分类号： G06G7/12 , G06N3/063 , H01L21/00
摘要： PROBLEM TO BE SOLVED: To perform a maximum or minimum value retrieval operation fast and also with high accuracy with respect to a vector quantization processor by adjusting the current drive capability of a multiple loop circuit in accordance with the change of an output of a logical operation circuit. SOLUTION: A differential absolute value distance signal 601 is stored as an electric charge on respective floating gates 602 of a νMOS comparator 603. An output of an OR gate 608 is fed back to a reference voltage signal input terminal 612 of all comparators 603 through variable resistor 611 that is controlled by a high gain amplifier 609 and a controller 610. They forms a ring oscillator of a multiple loop. A current drive capability that drives input capacitance of the comparators 603 is changed by switching the value of the resistor 611 and a sweep speed of reference voltage VR is controlled. The sweep speed of the VR is successively reduced by increasing the value of the resistor 611 gradually and retrieval accuracy is increased little by little.

39. 发明专利

JPH1196276A SEMICONDUCTOR ARITHMETIC CIRCUIT 失效
公开(公告)号：JPH1196276A
公开(公告)日：1999-04-09
申请号：JP25701597
申请日：1997-09-22
申请人： SHIBATA SUNAO , OMI TADAHIRO , ULTLA CLEAN TECHNOLOGY KAIHATS
发明人： SHIBATA SUNAO , NAKADA AKIRA , YODA MASAHIRO , OMI TADAHIRO , NITTA TAKEHISA
IPC分类号： G06G7/14 , H01L21/8238 , H01L27/092 , H03F3/70
摘要： PROBLEM TO BE SOLVED: To attain quick and highly accurate analog vector operation without requiring a complicated control circuit by providing respective gate electrodes with switch elements to switch inputs. SOLUTION: Conducted switch elements 121, 124, 126, 128 are interrupted and switch elements 122, 123, 125, 127 are conducted. The potential levels of respective input electrodes 117 to 120 are respectively made equal to ground potential, power supply potential, the potential of an input electrode 129, and the potential of the electrode 129. After electrically floating gate electrodes, the original states of the input electrodes 117 to 120 are respectively switched to ground potential, power supply potential, the input potential, and the input potential. Since mutual differences of plural input data can be obtained and a large value can be selected from the difference results, the absolute value of a difference of finally inputted data can be highly accurately computed at real time.

40. 发明专利

JPH10260817A SEMICONDUCTOR ARITHMETIC CIRCUIT, AND DTA PROCESSOR 失效
公开(公告)号：JPH10260817A
公开(公告)日：1998-09-29
申请号：JP8187797
申请日：1997-03-15
申请人： SHIBATA SUNAO , OMI TADAHIRO
发明人： MORIMOTO TATSURO , SHIBATA SUNAO , OMI TADAHIRO
IPC分类号： G06F7/02 , G06G7/12 , G06N3/063 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H03K19/20
摘要： PROBLEM TO BE SOLVED: To compare the sizes of plural pieces of data at a high speed by using a simple circuit in real time, by specifying a position where maximum voltage exists among signal voltage inputted to an inverter circuit group by the output signal of the inverter circuit group. SOLUTION: Since a vMOS(vertical MOS) cell B221 maintains an inversion state when '1' is inputted to even one of V1 -V4 , VR continuously reduces until the output of the last vMOS cell A218 changes from '1' to '0'. When the output of the vMOS cell A218 becomes '0', the vMOS cell B221 inverts the state and VR starts increasing to '1'. Since VR is decided so that the vMOS cell A218 of maximum input oscillates near a threshold, the oscillation of the circuit is formed to always contain the vMOS cell A218 of maximum input. Thus, the position of largest input voltage can continuously in time be specified.

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