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21. 发明专利

JP4043703B2 Semiconductor device, microcomputer, and flash memory 有权
公开(公告)号：JP4043703B2
公开(公告)日：2008-02-06
申请号：JP2000267044
申请日：2000-09-04
申请人：株式会社ルネサステクノロジ
发明人：裕品川 , 貴志山木 , 充平木 , 利広田中 , 幹竹内 , 正道藤戸
IPC分类号： G11C17/00 , G11C29/56 , G11C5/00 , G11C7/00 , G11C11/413 , G11C11/56 , G11C16/02 , G11C16/06 , G11C16/28 , G11C16/30 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/14 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L31/0336
CPC分类号： G11C29/50008 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/28 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

22. 发明专利

JP4022392B2 Semiconductor memory device and a method of testing as well as test circuit 有权
公开(公告)号：JP4022392B2
公开(公告)日：2007-12-19
申请号：JP2001377889
申请日：2001-12-11
申请人： Necエレクトロニクス株式会社
发明人：祥三内田 , 秀雄稲葉 , 弘行高橋
IPC分类号： G01R31/28 , G11C29/08 , G01R31/3185 , G11C8/18 , G11C11/401 , G11C11/403 , G11C11/406 , G11C29/14
CPC分类号： G11C29/12015 , G11C8/18 , G11C11/401 , G11C11/406 , G11C29/14

23. 发明专利

JP3956111B2 Semiconductor memory device and a method of testing the same 有权
公开(公告)号：JP3956111B2
公开(公告)日：2007-08-08
申请号：JP2002141266
申请日：2002-05-16
申请人：株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人：祥熏洪 , 始弘金
IPC分类号： G01R31/28 , G11C29/56 , G11C11/401 , G11C29/00 , G11C29/08 , G11C29/14 , G11C29/44 , G11C29/50
CPC分类号： G11C29/028 , G11C11/401 , G11C29/14 , G11C29/50 , G11C29/50012

24. 发明专利

JP3943890B2 Semiconductor device 有权
公开(公告)号：JP3943890B2
公开(公告)日：2007-07-11
申请号：JP2001320908
申请日：2001-10-18
申请人：富士通株式会社
发明人：和宏北崎
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G11C29/00 , G11C29/14 , G11C29/46
CPC分类号： G01R31/3172 , G01R31/31713 , G01R31/31723 , G11C29/46

25. 发明专利

JP3938801B2 Semiconductor memory device 失效
标题翻译：空值
公开(公告)号：JP3938801B2
公开(公告)日：2007-06-27
申请号：JP8329397
申请日：1997-03-17
申请人：株式会社ルネサステクノロジ
发明人：一昌安藤 , 恵津子川口 , 恵一日下田 , 康弘藤村
IPC分类号： G11C11/413 , G11C29/14

26. 发明专利

JP3880948B2 To test a group of memory that is independent on the function, replace the defective memory-word system 有权
公开(公告)号：JP3880948B2
公开(公告)日：2007-02-14
申请号：JP2003158551
申请日：2003-06-03
申请人：インフィネオンテヒノロギーズアーゲーInfineon TechnologiesAG
发明人：ボリシモーヌ , キルムザーステファン
IPC分类号： G01R31/28 , G11C29/12 , G11C11/413 , G11C29/00 , G11C29/14 , H01L21/66
CPC分类号： G11C29/808 , G11C29/14 , G11C29/846

27. 发明专利

JP2007018710A Semiconductor device and method of testing the same 审中-公开
标题翻译：半导体器件及其测试方法
公开(公告)号：JP2007018710A
公开(公告)日：2007-01-25
申请号：JP2006240081
申请日：2006-09-05
申请人： Fujitsu Ltd , 富士通株式会社
发明人： TSUBOI KOUKEI , FUJIOKA SHINYA
IPC分类号： G11C29/14 , G01R31/28 , G01R31/3185 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of testing the same, wherein a test mode entry can easily and securely be performed without making circuits in the semiconductor device large in scale nor lowering the degree of integration without reference to whether the semiconductor device is a synchronous type or an asynchronous type.
SOLUTION: The semiconductor device having a test mode for conducting a test is equipped with a first circuit that generates a first signal based upon a first dummy command signal inputted a plurality of times, and a second dummy command signal and a third dummy command signal different from the first dummy command signal and generates a second signal designating an entry into a corresponding test mode or an exit from the corresponding test mode based upon the first signal.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体器件及其测试方法，其中可以容易且可靠地执行测试模式输入，而不会使半导体器件中的电路大规模地进行而不降低集成度而无需参考涉及半导体器件是同步型还是异步型。解决方案：具有用于进行测试的测试模式的半导体器件配备有基于多次输入的第一虚拟命令信号产生第一信号的第一电路和第二虚拟命令信号和第三虚拟命令信号，并且基于第一信号产生指定相应测试模式的条目的第二信号或者从相应测试模式退出的第二信号。版权所有（C）2007，JPO＆INPIT

28. 发明专利

JP3862306B2 失效
公开(公告)号：JP3862306B2
公开(公告)日：2006-12-27
申请号：JP30957695
申请日：1995-11-28
IPC分类号： G11C11/403 , G11C29/14 , G06F1/04 , G06F1/08 , G11C11/401 , G11C11/406 , G11C11/4076 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/50

29. 发明专利

JP2006344279A SEMICONDUCTOR DEVICE AND TESTING METHOD 审中-公开
公开(公告)号：JP2006344279A
公开(公告)日：2006-12-21
申请号：JP2005168274
申请日：2005-06-08
申请人： ELPIDA MEMORY INC
发明人： MAEDA KAZUNORI
IPC分类号： G11C29/50 , G01R31/28 , G11C11/401 , G11C11/407 , G11C29/14
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device facilitating identification of cause of defects, such as whether deterioration of characteristics, defects, etc., at evaluation and analysis are caused by a frequency synchronizing circuit. SOLUTION: The device is equipped with a DLL circuit 10 for inputting external clock signals from external clock terminals 13, 14 and producing signals synchronized with these external clock signals; and a selector 11 for inputting a clock signal inputted from an external terminal 15 and an output signal from the DLL circuit 10, and for outputting the clock signal inputted from the external terminal 15 at the test, based on a test mode signal and outputting the output signal from the DLL circuit 10 at normal operation times. COPYRIGHT: (C)2007,JPO&INPIT

30. 发明专利

JP3854159B2 有权
公开(公告)号：JP3854159B2
公开(公告)日：2006-12-06
申请号：JP2002014707
申请日：2002-01-23
IPC分类号： G01R31/28 , G11C29/04 , G11C8/16 , G11C29/14 , H01L21/66

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