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21. 发明专利

JPH0548408A DIGITAL INPUT CIRCUIT 失效
公开(公告)号：JPH0548408A
公开(公告)日：1993-02-26
申请号：JP20280691
申请日：1991-08-13
申请人： OMRON TATEISI ELECTRONICS CO
发明人： ASAKAWA HIDEO
IPC分类号： H03K5/1254 , H03K5/01
摘要： PURPOSE:To select a frequency of a filter clock precisely even when a signal width of an input signal is switched by a contact or the like while devising the circuit such that a proper clock corresponding to a width of an input signal is selected automatically based on the width of the input signal. CONSTITUTION:Two filter circuits 20,22 are connected in series. The one filter circuit 20 is operated in response to a high speed filter clock CK1 and the other filter circuit 22 is operated in response to a low speed filter clock CK2 respectively. Moreover, an output signal from the 1st filter circuit 20 relating to the high speed input signal is counted by a 1st counter 26, the count is outputted as a valid signal, and as to an input signal including chattering, the chattering is eliminated by setting a sampling time of a 2nd counter 28 so as to eliminate the chattering and the resulting signal is outputted as a valid signal, and a valid signal from a low speed input signal is obtained by the 2nd filter circuit 22.

22. 实用新型

JPH0450657Y2 失效
公开(公告)号：JPH0450657Y2
公开(公告)日：1992-11-30
申请号：JP7424387
申请日：1987-05-18
IPC分类号： H03K17/16 , H03K5/01 , H03K5/1254

23. 发明专利

JPH04145715A CHATTERING PREVENTION CIRCUIT 失效
公开(公告)号：JPH04145715A
公开(公告)日：1992-05-19
申请号：JP26987190
申请日：1990-10-08
申请人： NIPPON ELECTRIC IC MICROCOMPUT
发明人： ISODA MICHIO
IPC分类号： H03K5/1254 , H03K5/01
摘要： PURPOSE:To prevent malfunction due to chattering and also the malfunction due to chattering whose charging time is longer than the discharge time by discharging a capacitor rapidly for a discharge time. CONSTITUTION:A comparator 12 is inverted, an NPN transistor(TR) 22 is turned on and a current depending on a resistor 23 for current limit flows through a current mirror circuit comprising PNP TRs 24,25. Thus, a current flows rapidly to a base on an NPN TR 9 to discharge a capacitor 11 rapidly and after the inversion of the comparator 12, the circuit is operated in a sufficiently faster discharge time than the charging time. Then with an external switch 18 turned off, when the comparator 12 is inverted, the NPN TR 22 is turned off and the capacitor 11 is charged/discharged in a charge/discharge time of the capacitor 11 to be set. As a result, malfunction of chattering is prevented and malfunction due to chattering whose charging time is longer than the discharge time is prevented.

24. 发明专利

JPH0429249B2 失效
公开(公告)号：JPH0429249B2
公开(公告)日：1992-05-18
申请号：JP5499682
申请日：1982-04-02
IPC分类号： G10H1/18 , G10H1/057 , H03K5/1252 , H03K5/1254 , H03K23/00

25. 发明专利

JPH04132413A CHATTERING PREVENTION CIRCUIT AND CLOCK GENERATING CIRCUIT 失效
公开(公告)号：JPH04132413A
公开(公告)日：1992-05-06
申请号：JP25489890
申请日：1990-09-25
申请人： NEC CORP
发明人： YAMASHITA HIROSHI
IPC分类号： H03K5/00 , H03K5/01 , H03K5/1254
摘要： PURPOSE:To eliminate chattering caused by withdrawal of a connector or the like and to prevent adverse effect on a succeeding device by using a signal outputted from an AND circuit as an output signal. CONSTITUTION:Interrupt detection circuits 41,42 receive respectively output signals of chattering prevention circuits 101,102 and output a low level selector control signal to a 2-1 selector 5 when the circuits 41,42 receive a clock signal continuously and output a high level selector control signal to the selector when the circuits 41,42 receive no clock signal for a prescribed time or over. When a connector 103 is withdrawn and chattering takes place, monostable multivibrators 2,3 are both triggered for a short period and output a pulse in which a high level is consecutive for a longer timer than usual. An output of an OR circuit 7 goes to a high level for the time and an output of an inverting circuit 8 goes to a low level on the other hand, then the output of an AND circuit 9 keeps a low level. Thus, chattering takes place in the clock signal by the withdrawal of the connector, but the chattering is masked in the output of a chattering prevention circuit 101 and eliminated.

26. 发明专利

JPH0477111A CHATTERING NOISE ABSORPTION CIRCUIT 失效
公开(公告)号：JPH0477111A
公开(公告)日：1992-03-11
申请号：JP18855990
申请日：1990-07-17
申请人： NEC CORP , MIYAGI NIPPON DENKI KK
发明人： MORIYA TOMOHIRO , YUKI KAZUHIRO
IPC分类号： H03K5/1254 , H03K5/01
摘要： PURPOSE:To stably absorb noises even when any kind of chattering noise is generated in time width by absorbing the noises in constant time width instead of deciding time constant and hysteresis width while estimating the noise components in a certain range to absorb the noises. CONSTITUTION:When inputting an input signal (IN) including the chattering noise, a multivibrator 1 starts at the rising, and outputs the pulse signal (signal 'b') of time width T 1. On the other hand, a reversing circuit 3 outputs a logical value reversing signal (signal (a)) of the input signal (IN). A multivivibrator 2 starts at the rising of the signal (b,) only when the signal 5a) is low level, and outputs the pulse signal of time width T2 (output signal OUT). In short, the chattering noise can be eliminated by the multivibrator 1, and the pulse signal of required time width is obtained.

27. 发明专利

JPH03297216A DIGITAL VALUE CHATTERING DECIDING DEVICE 失效
公开(公告)号：JPH03297216A
公开(公告)日：1991-12-27
申请号：JP9776990
申请日：1990-04-16
申请人： TOSHIBA CORP
发明人： ISHINO MAKOTO
IPC分类号： H03K5/1254 , H03K5/01
摘要： PURPOSE:To allow the device to take countermeasures against chattering only through the setting of a dead time of a computer by recognizing and deciding it to be chattering when an input of consecutive 1s takes place in excess of a prescribed dead time after the input changes from '0' to '1'. CONSTITUTION:A fetch means 4 in a state monitor installation control computer 3 being a host device to a manufacture installation 2 fetches digital signals on plural channels from a digital signal detection notice device 1 of the installation 2. Then the device 1 compares the signals with digital signals fetched precedingly. As a result, the signal changes from '0' to '1' deciding means 5 discriminates the state to be a chattering based on a dead time of a channel dependent dead time file 7 registered in advance by a dead time setting means 6 and the state decision as to whether or not the current time is in a dead time. A notice means 8 informs the result of decision of the digital value of each channel to a state monitor control means 9. Thus, only the control computer located to be a host device of various manufacture installations 2 copes flexibly with the state change such as introduction of a new installation or a signal change.

28. 发明专利

JPH03263914A SIGNAL WAVEFORM SHAPING CIRCUIT 失效
公开(公告)号：JPH03263914A
公开(公告)日：1991-11-25
申请号：JP6326290
申请日：1990-03-14
申请人： FUJITSU LTD
发明人： TANIGUCHI KIYOSHI
IPC分类号： H03K5/1254 , H03K5/01 , H03K17/16
摘要： PURPOSE:To sufficiently remove noise superimposed when the logic level of input is fixed by inputting an input signal and the output of a first flip-flop, performing switching control so as to compute OR logic or AND logic corresponding to the output signal of a second flip-flop, and inputting a result to the second flip-flop. CONSTITUTION:Noise with negative polarity superimposed when the 'H' level of the input signal IN continues is blocked with a gate means 2 set at the OR logic due to the 'H' level of the output signal, and it is not transmitted to the second flip-flop 3. Also, a noise with positive polarity superimposed when the 'L' level of the input signal IN continues is blocked with the gate means 2 set at the AND logic due to the 'L' level of the output signal, and it is not transmitted to the second flip-flop 3. Therefore, no inversion of the second flip-flop occurs even when those noises are generated at the rise time of a clock, and no noise appears on the output signal, thereby, whole nose appearing when the input signal rises or falls and the 'H' and 'L' levels are set at fixed logic can be removed.

29. 发明专利

JPH0369215B2 失效
公开(公告)号：JPH0369215B2
公开(公告)日：1991-10-31
申请号：JP22024482
申请日：1982-12-17
申请人： TOSHIBA KK , TOSHIBA GARASU KK
发明人： ABE YUKITO , ANNO GOSUKE , NISHIJIMA KATSUJI
IPC分类号： H03K17/60 , G01K7/00 , H03K5/1254 , H03K17/00

30. 实用新型

JPH0384642U 失效
公开(公告)号：JPH0384642U
公开(公告)日：1991-08-28
申请号：JP14602689
申请日：1989-12-19
IPC分类号： H01H9/54 , H03K5/01 , H03K5/1254 , H03K17/00 , H03K17/78

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