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21. 发明专利

JP2007504742A Robust de-interlacing of video signal 审中-公开
公开(公告)号：JP2007504742A
公开(公告)日：2007-03-01
申请号：JP2006525243
申请日：2004-08-25
申请人：コニンクリユケフィリップスエレクトロニクスエヌ.ブイ.
发明人：ハーンヘラルドデ
IPC分类号： H04N7/01 , H04N5/44
CPC分类号： H04N7/0135 , H04N7/012 , H04N7/014
摘要：本発明は、ビデオ信号をデインタレースする方法であって、画素の第１のセット及び画素の第２のセットから第１の画素サンプルを補間するステップ（２４）と、前記画素の第１のセット及び画素の第３のセットから第２の画素サンプルを補間するステップ（２６）と、前記画素の第１のセットの画素から第３の画素サンプルを算出するステップ（２８）と、前記第１の画素サンプルと前記第２の画素サンプルとの間の関係を算出するステップ（３０）と、を有する方法に関する。補間を改善し画質を改善するため、前記第１の画素サンプル、前記第２の画素サンプル、前記第３の画素サンプル及び前記第１の画素サンプルと前記第２の画素サンプルとの間の前記関係に基づいて、出力画素サンプルを算出することが提案される。

22. 发明专利

JP3837690B2 The video signal processing apparatus 有权
公开(公告)号：JP3837690B2
公开(公告)日：2006-10-25
申请号：JP34429299
申请日：1999-12-03
申请人：パイオニア株式会社
发明人：正則星川
IPC分类号： G09G5/00 , H04N5/66 , G06T3/40 , G09G5/391 , H04N5/14 , H04N5/46 , H04N7/01
CPC分类号： H04N7/0135 , G06T3/40 , H04N5/14 , H04N5/44 , H04N5/46
摘要： The present invention provides a video processor which has a simple circuit configuration and can scale up and down image resolution freely. A video signal processor includes a plurality of line memories, each storing one horizontal scanning line of video data series, a controller for controlling writing and reading operations of input video data series in the line memories for every horizontal scanning line, and an arithmetical unit for generating a new horizontal scanning line of video data series based on video data series from two line memories. The controller selects the vertical scaling power of the resolution, and generates a horizontal scanning synchronizing signal having a period depending on the selected scaling power. The arithmetical unit is triggered by the horizontal scanning synchronizing signal and generates a new video data series.

23. 发明专利

JP2005507618A Interpolation of the edge-oriented video data 审中-公开
公开(公告)号：JP2005507618A
公开(公告)日：2005-03-17
申请号：JP2003541268
申请日：2002-10-18
申请人：コーニンクレッカフィリップスエレクトロニクスエヌヴィKoninklijke Philips Electronics N.V.
发明人：ハーンジェラルドデ , ロジェルロッダー
IPC分类号： H04N5/44 , H04N7/01
CPC分类号： H04N7/014 , H04N7/012 , H04N7/0135 , H04N7/0137
摘要：本発明は、エッジに沿ったビデオ画像内のピクセルの補間時のエラー低減のための方法に関する。２つの補間法の出力（４、６）を結合することによって、及び１つの補間法の出力のみを用いる混合ファクタ（ｋ）を計算することによって、補間の結果が改善され得る。第２の補間法により得られるピクセルの方向にエッジ依存の補間の推定エラーを適用する場合、上記出力が向上される。

24. 发明专利

JP2004336608A Method and circuit for converting image data, and electronic camera 有权
公开(公告)号：JP2004336608A
公开(公告)日：2004-11-25
申请号：JP2003132726
申请日：2003-05-12
申请人： Sony Corp , ソニー株式会社
发明人： KUME TSUTOMU , YAMADA TOKUICHIRO
IPC分类号： H04N5/232 , H04N7/01 , H04N11/20 , H04N101/00
CPC分类号： H04N7/0135
摘要： PROBLEM TO BE SOLVED: To provide a system conversion circuit for image data whose movement is smooth.
SOLUTION: A circuit for converting image data is provided with: a memory 16 in which image data of a moving picture of an NTSC system is written; a circuit 14 for taking out a signal required to prepare image data for odd fields and even fields in a PAL system from the memory 16; circuits 73 and 74 for converting the extracted image data into first and second image data of a line frequency in the PAL system; a circuit 75 for mixing image data of the odd fields among the first and second image data in a prescribed ratio to output the mixed data as image data of the odd fields in the PAL system and also mixing image data of the even fields in a prescribed ratio to output the mixed data as image data of the even fields in the PAL system; and a fourth circuit 77 for changing ratios for mixture for each field period in the PAL system.
COPYRIGHT: (C)2005,JPO&NCIPI

25. 发明专利

JP2004527171A Improvement of scalable resolution of the video image 审中-公开
公开(公告)号：JP2004527171A
公开(公告)日：2004-09-02
申请号：JP2002577418
申请日：2002-03-19
申请人：コーニンクレッカフィリップスエレクトロニクスエヌヴィKoninklijke Philips Electronics N.V.
发明人：ラン，ツェ−ホア
IPC分类号： H04N5/205 , G06T3/40 , G06T5/00 , H04N5/14 , H04N5/208 , H04N5/46 , H04N7/01 , H04N11/00 , H04N21/4402
CPC分类号： H04N7/0125 , G06T3/403 , G06T5/003 , G06T5/008 , G06T7/13 , G06T2207/10016 , G06T2207/20012 , G06T2207/20192 , H04N5/142 , H04N5/208 , H04N5/46 , H04N7/012 , H04N7/0135 , H04N11/002 , H04N21/440218
摘要： A system and method for enhancing resolution in a video image includes acquiring a relatively low resolution video signal and applying a peaking function and analyzing the peaked signal to identify potential edges. The low resolution signal is then upconverted to a higher resolution format. Actual edges in the image are detected and linked in the higher resolution format, and a luminance transition improvement function is applied to the edges to sharpen the image. Analysis of the image while at low resolution reduces computation time, yet still produces a high quality output image.

26. 发明专利

JP2004236194A Video data recorder and video data recording method 审中-公开
公开(公告)号：JP2004236194A
公开(公告)日：2004-08-19
申请号：JP2003024856
申请日：2003-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： MARUYAMA KOJI , MIZUSAWA TSUTOMU
IPC分类号： G11B20/10 , G11B20/12 , G11B27/034 , H04N5/445 , H04N5/46 , H04N5/765 , H04N5/781 , H04N5/85 , H04N5/91 , H04N5/93 , H04N7/01 , H04N9/804 , H04N11/20
CPC分类号： H04N7/0135 , G11B27/034 , G11B2220/218 , G11B2220/2516 , G11B2220/2562 , G11B2220/455 , H04N5/4401 , H04N5/46 , H04N5/781 , H04N5/85 , H04N7/01 , H04N9/8042 , H04N11/20 , H04N21/42646 , H04N21/42661 , H04N21/4325 , H04N21/4334 , H04N21/440218
摘要： PROBLEM TO BE SOLVED: To record video signals of broadcast systems different from each other in a digital signal recording medium such as an optical disk by efficiently converting them into signals of another broadcast system. SOLUTION: Video data recorded in an HDD 6 is converted into video data in other broadcast system different from that of the video data by a broadcast system conversion part 9 after it is decoded. Data complement is performed to the converted video data by a frame synchronizer 3 and recorded in a DVD after it is compressed. COPYRIGHT: (C)2004,JPO&NCIPI

27. 发明专利

JP2004228775A Frame conversion method, frame conversion circuit, and electronic camera 有权
标题翻译：框架转换方法，框架转换电路和电子摄像机
公开(公告)号：JP2004228775A
公开(公告)日：2004-08-12
申请号：JP2003012499
申请日：2003-01-21
申请人： Sony Corp , ソニー株式会社
发明人： KUME TSUTOMU , ISHII SHINYA , YAMADA TOKUICHIRO , TOMITA YOSHINORI
IPC分类号： H04N7/01
CPC分类号： H04N7/0135
摘要： PROBLEM TO BE SOLVED: To provide an electronic camera having functions of recording/playing motion pictures, which enables frame conversion with smooth motion in converting the frame, in particular from an NTSC system to a PAL system.
SOLUTION: A memory 16 in which frame image data of the NTSC system is written is provided. A circuit for picking out image data of odd-numbered fields and even-numbered fields from the memory 16 per odd-numbered field period and even-numbered field period during a frame period of the PAL system is provided. A circuit 76 is provided for mixing the image data in an odd-numbered field picked up by the circuit with the image data in a subsequent odd-numbered field at a predetermined ratio to output them as the image data in the odd-numbered fields in the PAL system frame period, and mixing the image data in a picked-up even-numbered field with the image data of a subsequent even-numbered field at a predetermined ratio for outputting them as the image data in the even-numbered fields in the PAL system frame period. A circuit 73 for changing the ratio of mixing in the circuit 76 per PAL system field period is provided.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有记录/播放运动图像的功能的电子照相机，这使得能够在将帧转换成平滑运动的帧转换，特别是从NTSC系统到PAL系统。解决方案：提供其中写入NTSC制式的帧图像数据的存储器16。提供了一种用于在PAL系统的帧周期期间从每个奇数场周期和偶数场周期中从存储器16拾取奇数场和偶数场的图像数据的电路。提供电路76，用于将由电路拾取的奇数场中的图像数据以预定比率的后续奇数场中的图像数据混合，以将其作为奇数场中的图像数据输出 PAL系统帧周期，并将拾取的偶数场中的图像数据与随后的偶数场的图像数据以预定比率混合，以将它们作为图像数据输出到偶数场中 PAL系统帧周期。提供了一种用于根据PAL系统场周期改变电路76中的混合比的电路73。版权所有（C）2004，JPO＆NCIPI

28. 发明专利

JP2004104636A Data processing unit and data processing method, recording medium and program 有权
标题翻译：数据处理单元和数据处理方法，记录介质和程序
公开(公告)号：JP2004104636A
公开(公告)日：2004-04-02
申请号：JP2002266328
申请日：2002-09-12
申请人： Sony Corp , ソニー株式会社
发明人： KONDO TETSUJIRO , NISHIKATA TAKEHARU , CHIKAOKA SHIZUO , YAMAMOTO SAKON
IPC分类号： H04N5/44 , H04N7/01 , H04N7/34
CPC分类号： H04N7/0135 , H04N7/0145 , H04N19/122 , H04N19/162 , H04N19/176 , H04N19/40 , H04N19/587 , H04N19/593 , H04N19/645 , H04N19/85
摘要： PROBLEM TO BE SOLVED: To enable converting an input data to a data of a different format, and thereafter converting into a signal on which orthogonal conversion is performed. SOLUTION: A block extraction section 31 extracts a class tap from a composite signal. A pixel location mode output section 32 decides a pixel location mode from the extracted class tap, and outputs to a coefficient memory 33. A coefficient operation section 37 acquires a type coefficient from a type coefficient memory 36, operates a predicted coefficient based on a conversion scheme selection signal input from a designation section 38, and stores the predicted coefficient into the coefficient memory 33. The coefficient memory 33 supplies the predicted coefficient corresponding to the pixel location mode to a prediction operation section 35. A block extraction section 34 extracts a predicted tap from the composite signal, and output the prediction operation section 35. The prediction operation section 35 outputs a component signal or a component conversion signal based on the predicted tap and the predicted coefficient. The method and unit are applicable to a television receiver. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了能够将输入数据转换为不同格式的数据，然后转换为执行正交转换的信号。解决方案：块提取部分31从复合信号中提取类别抽头。像素位置模式输出部分32从所提取的类别抽头确定像素位置模式，并将其输出到系数存储器33.系数运算部分37从类型系数存储器36获取类型系数，根据转换操作预测系数方案选择信号从指定部分38输入，并将预测系数存储到系数存储器33.系数存储器33将与像素位置模式相对应的预测系数提供给预测操作部分35.块提取部分34提取预测系数从复合信号中抽出，并输出预测运算部35.预测运算部35基于预测抽头和预测系数输出分量信号或分量变换信号。该方法和单元适用于电视接收机。版权所有（C）2004，JPO

29. 发明专利

JP2004093834A Video signal processor and integrated circuit 有权
标题翻译：视频信号处理器和集成电路
公开(公告)号：JP2004093834A
公开(公告)日：2004-03-25
申请号：JP2002253956
申请日：2002-08-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： SENDA KAZUNORI
IPC分类号： H04N5/14 , G09G5/00 , G09G5/391 , G09G5/397 , G09G5/399 , H04N1/393 , H04N5/66 , H04N7/01
CPC分类号： H04N7/0135
摘要： PROBLEM TO BE SOLVED: To prevent writing and reading out of line memories from being reversed with a video signal processor and an integrated circuit.
SOLUTION: The video signal processor has a plurality of the line memories for successively writing inputted video signal data in line units, a timing control means for controlling the writing timing of the video signal data to the plurality of the line memories and the reading out timing of the video signal data from the plurality of the line memories, and an arithmetic output means for outputting the video signal data varying in the resolution defined by the number of pixels in a horizontal direction and the number of lines in the vertical direction by subjecting the video signal data read out of the plurality of the line memories to arithmetic processing. The above processor is provided with a line control means for varying the number of pixels of the prescribed lines of the video signal data obtained from the arithmetic output means according to the conversion rate of the resolution of the video signal data.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了防止写入和读出行存储器与视频信号处理器和集成电路相反。解决方案：视频信号处理器具有多个行存储器，用于以行单位连续写入输入的视频信号数据;定时控制装置，用于控制视频信号数据对多个行存储器的写入定时，从多个行存储器读出视频信号数据的定时;以及算术输出装置，用于输出以水平方向上的像素数量和垂直方向上的行数定义的分辨率变化的视频信号数据通过使从多个行存储器读出的视频信号数据进行运算处理。上述处理器设置有线控制装置，用于根据视频信号数据的分辨率的转换率来改变从算术输出装置获得的视频信号数据的规定行的像素数。版权所有（C）2004，JPO

30. 发明专利

JP2004032708A Apparatus for detecting image angle and scanning line interpolating apparatus having the same 有权
公开(公告)号：JP2004032708A
公开(公告)日：2004-01-29
申请号：JP2003123406
申请日：2003-04-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KAWAMURA HIDEAKI , KASAHARA MITSUHIRO , OOKI TOMOAKI
IPC分类号： G06T3/40 , G06T7/00 , G06T7/60 , H04N5/14 , H04N7/01
CPC分类号： G06T3/403 , H04N5/142 , H04N7/012 , H04N7/0135 , H04N7/0142
摘要： PROBLEM TO BE SOLVED: To provide an apparatus for detecting image angle for accurately detecting the angle and shape of an image being displayed by an image signal.
SOLUTION: A binarization section 2 binarizes a picture signal VDI inputted from an A/D converter 7 and an image signal VD2, outputted from a line memory 1a with an average brightness signal LU given from a section 5 for processing image signals in a detection window set as a threshold, and outputs a binarization pattern BI. A reference pattern generation section 6 generates a plurality of reference patterns RA. An angle detection section 3 compares the binarization pattern BI with each of the plurality of reference patterns RA, and outputs the angle of the matched reference pattern RA as angle information S1. An arc shape detection section 4 outputs angle information T1 and arc shape information T2 in the edge of images from the combination of pieces of angle information S1, S2, S3 in an interpolation scanning line, including a target interpolation pixel and a scanning line between interpolation scanning lines one which is above and one which is below.
COPYRIGHT: (C)2004,JPO

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