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21. 发明专利

JP5634742B2 半導体装置の製造方法有权
公开(公告)号：JP5634742B2
公开(公告)日：2014-12-03
申请号：JP2010105392
申请日：2010-04-30
申请人：ピーエスフォールクスコエスエイアールエルPS4 Luxco S.a.r.l. , ピーエスフォールクスコエスエイアールエルPS4 Luxco S.a.r.l.
发明人：孝神作 , 孝神作
IPC分类号： H01L21/768 , C23C14/06 , H01L21/3205 , H01L23/532
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/76882 , H01L23/53223 , H01L2924/0002 , H01L2924/00

22. 发明专利

JP2014514734A Off-angle heating of the lower surface of the substrate using a lamp assembly 有权
公开(公告)号：JP2014514734A
公开(公告)日：2014-06-19
申请号：JP2013558073
申请日：2012-03-09
申请人：アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人：モーリスイーエワート , アナンサケイスブラマニ , ウメッシュエムケルカー , チャンドラセカーバラスブラマンヤン , ジョセフエムラニッシュ
IPC分类号： H01L21/26 , C23C14/58 , C23C16/56 , H01L21/205 , H01L21/28 , H01L21/285 , H01L21/31
CPC分类号： C23C14/5806 , C23C14/34 , C23C14/3435 , C23C14/541 , C23C16/4581 , C23C16/481 , H01J37/3411 , H01J37/3488 , H01L21/02104 , H01L21/28518 , H01L21/2855 , H01L21/324 , H01L21/67115 , H01L21/67248 , H01L21/68742 , H01L21/76882
摘要：基板を処理する方法及び装置を開示する。装置は、基板上への材料処理と熱処理の両方共に行うことができる二重機能チャンバである。チャンバは、チャンバの処理位置と搬送位置の間に配置された環状の放射源を有する。リフトピンは、基板の放射加熱を供給するために基板支持体が放射源平面よりも下に下がっている間、処理位置に基板を維持するに十分な長さを有する。その第１の面に形成された開口を有する基板を処理する方法は、第１の面上の開口に材料を堆積させる段階と、第１の面の反対側の第２の面を加熱することにより材料をリフローさせる段階とを含む。第２の材料をその後に堆積させることができ、開口を部分的に又は完全に充填する。代替的に、循環的な堆積／リフロー処理を行うことができる。
【選択図】図１

23. 发明专利

JP2013143442A Device manufacturing method and manufacturing device 审中-公开
标题翻译：装置制造方法和制造装置
公开(公告)号：JP2013143442A
公开(公告)日：2013-07-22
申请号：JP2012002305
申请日：2012-01-10
申请人： Ulvac Japan Ltd , 株式会社アルバック
发明人： ENDO YOHEI , KODAIRA SHUJI , SAKAMOTO YUTA , HAMAGUCHI JUNICHI , UCHIDA YOHEI , HIGUCHI YASUSHI , NAKAMURA SHINYA , HASHIMOTO KAZUYOSHI , IKEDA YOSHIHIRO , IWASAWA HIROAKI
IPC分类号： H01L21/768 , C23C14/34 , H01L21/28 , H01L21/3205 , H01L23/532
CPC分类号： H01L21/76882 , H01L21/76883
摘要： PROBLEM TO BE SOLVED: To provide a device manufacturing method capable of forming a conductive film by embedding a conductive material in a fine recess provided on one surface of a substrate without any space.SOLUTION: A device manufacturing method is a deposition method comprising at least a first step of forming a barrier film 103 so as to cover at least an inner wall surface 102a of a recess provided on one surface 101a of a substrate 101 with respect to the substrate 101, a second step of forming a conductive film 104 so as to cover the barrier film 103, and a third step of melting the conductive film 104 by a reflow method. This manufacturing method also includes a step α of exposing a substrate in which the barrier film 103 and the conductive film 104 were laminated in this order through the second step in a pressure A atmosphere only for a time B between the second step and the third step. The method controls the step α so that a product of the pressure A and the time B becomes less than or equal to 6×10[Pa s] in the step.
摘要翻译：要解决的问题：提供一种能够通过将导电材料嵌入设置在基板的一个表面上的细小凹部中而形成导电膜的装置制造方法，而没有任何空间。装置制造方法是至少包括形成阻挡膜103以便覆盖相对于基板101设置在基板101的一个表面101a上的凹部的至少内壁表面102a的第一步骤，形成导电膜104的第二步骤以覆盖阻挡膜103，以及通过回流法熔化导电膜104的第三步骤。该制造方法还包括步骤α，其中通过第二步骤在压力A气氛中依次层叠阻挡膜103和导电膜104的基板，仅在第二步骤和第三步骤之间的时间B 。该方法控制步骤α，使得压力A和时间B的乘积在步骤中变得小于或等于6×10 [Pa s]。

24. 发明专利

JP2012074522A Film forming method and film forming device 有权
标题翻译：薄膜成型方法和薄膜成型装置
公开(公告)号：JP2012074522A
公开(公告)日：2012-04-12
申请号：JP2010217895
申请日：2010-09-28
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： ISHIZAKA TADAHIRO , SAKUMA TAKASHI , HATANO TATSUO , YOKOYAMA ATSUSHI , GOMI ATSUSHI , YASUMURO CHIAKI , FUKUSHIMA TOSHIHIKO , TOSHIMA HIROSHI , KAWAMATA SEIYA , MIZUSAWA YASUSHI , KATO TAKAYOSHI
IPC分类号： H01L21/3205 , C23C14/14 , H01L21/285 , H01L23/52
CPC分类号： H01L21/768 , C23C14/021 , C23C14/024 , C23C14/14 , C23C14/345 , C23C14/3492 , C23C14/541 , C23C14/542 , H01J37/34 , H01L21/2855 , H01L21/76865 , H01L21/76873 , H01L21/76877 , H01L21/76882
摘要： PROBLEM TO BE SOLVED: To provide a film forming method and a film forming device capable of forming a metal film in a recess to prevent a void or the like from occurring.SOLUTION: A film forming method for generating a metal ion from a metal target 76 by plasma in a processing container 22, pulling in the generated metal ion by a bias, and depositing a thin film of the metal on a workpiece on which a recess 4 is formed comprises: a base film formation step of generating a metal ion from a target, pulling in the metal ion by a bias, and forming a base film 90 in the recess; an etching step of ionizing a noble gas by a bias in the state in which no metal ion is generated, puling in the generated ion, and etching the base film; and film forming reflow step of generating a metal ion by plasma-sputtering the target, pulling in the generated metal ion by bias power, and reflowing this film 92 composed of a metal film by heating while accumulating this film.
摘要翻译：要解决的问题：提供能够在凹部中形成金属膜以防止发生空隙等的成膜方法和成膜装置。解决方案：一种用于在处理容器22中通过等离子体从金属靶76产生金属离子的薄膜形成方法，通过偏压拉动产生的金属离子，并将金属薄膜沉积在其上的工件上形成凹部4包括：基底膜形成步骤，从靶产生金属离子，通过偏压拉入金属离子，并在凹部中形成基膜90; 在不产生金属离子的状态下通过偏压离子化惰性气体的蚀刻步骤，在产生的离子中进行脉冲化，并蚀刻基膜; 以及成膜回流工序，通过等离子体溅射靶产生金属离子，通过偏置功率拉入所产生的金属离子，并在积聚该膜的同时通过加热回流由金属膜构成的膜92。版权所有（C）2012，JPO＆INPIT

25. 发明专利

JP2011233833A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011233833A
公开(公告)日：2011-11-17
申请号：JP2010105392
申请日：2010-04-30
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KAMISAKU TAKASHI
IPC分类号： H01L21/768 , C23C14/06 , H01L21/3205 , H01L23/52
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/76882 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device suppressing an increase in contact resistance without adding an extra step.SOLUTION: In the method for manufacturing the semiconductor device, a first Ti film, a TiN film, a second Ti film, a first Al film and a second Al film are formed in a contact hole provided in a second interlayer dielectric film on a Cu wiring in this order. When the first Ti film is formed, a ratio of the thickness of a first part on a bottom of the contact hole to the thickness of a second part on the second interlayer dielectric film (the fist part/the second part)≤0.05. The second Al film is formed by the aluminum reflow method, and in this case the second Ti film and the first Al film are formed as aluminum-titanium alloy films.
摘要翻译：要解决的问题：提供抑制接触电阻增加而不增加额外步骤的半导体器件。解决方案：在制造半导体器件的方法中，在设置在第二层间电介质膜中的接触孔中形成第一Ti膜，TiN膜，第二Ti膜，第一Al膜和第二Al膜在Cu布线上按顺序。当形成第一Ti膜时，接触孔底部的第一部分的厚度与第二层间电介质膜上的第二部分（第一部分/第二部分）的厚度的比值≥0.05。第二Al膜通过铝回流法形成，在这种情况下，第二Ti膜和第一Al膜形成为铝 - 钛合金膜。版权所有（C）2012，JPO＆INPIT

26. 发明专利

JP4554011B2 Manufacturing method of a semiconductor integrated circuit device 有权
公开(公告)号：JP4554011B2
公开(公告)日：2010-09-29
申请号：JP22687699
申请日：1999-08-10
申请人：ルネサスエレクトロニクス株式会社
发明人：伸郎大和田 , 直史大橋 , 日出山口 , 健一武田 , 純司野口 , 達之齋藤
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/28 , H01L21/321 , H01L21/3213 , H01L21/70 , H01L21/768 , H01L23/532
CPC分类号： H01L21/3212 , H01L21/02063 , H01L21/02074 , H01L21/3185 , H01L21/32136 , H01L21/67115 , H01L21/68792 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/7684 , H01L21/76882 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： After formation of Cu interconnections 46 a to 46 e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46 a to 46 e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

27. 发明专利

JP2009105289A METHOD OF FORMING Cu WIRING 审中-公开
标题翻译：形成铜线的方法
公开(公告)号：JP2009105289A
公开(公告)日：2009-05-14
申请号：JP2007276891
申请日：2007-10-24
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： HATANO TATSUO , GOMI ATSUSHI , MIZUSAWA YASUSHI , HARA MASAMICHI , SAKUMA TAKASHI
IPC分类号： H01L21/3205 , C23C14/14 , H01L21/768 , H01L23/52
CPC分类号： H01L23/485 , H01L21/2855 , H01L21/76846 , H01L21/76882 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of forming Cu wiring, capable of filling up Cu reliably even into a minute trench or hole.
SOLUTION: In forming a Cu wiring in a Low-k film 2 having a trench 3 formed on a silicon substrate 1 via a barrier layer 4, a layer 5 to be wet constituted by a metal material to wet with Cu is formed on the barrier layer 4 through CVD, a Cu layer 6 is formed on the layer 5 to be wet through PVD, and after forming the Cu layer 6, the silicon substrate 1 is heated to allow the Cu layer 6 to flow into the trench 3 to be filled with Cu.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成Cu布线的方法，其能够可靠地将Cu填充到微小的沟槽或孔中。解决方案：在经由阻挡层4形成在硅衬底1上的具有沟槽3的Low-k膜2中形成Cu布线时，形成由用Cu润湿的金属材料构成的湿气层5 通过CVD在阻挡层4上，通过PVD在层5上形成Cu层6，在形成Cu层6之后，加热硅衬底1使Cu层6流入沟槽3 充满铜。版权所有（C）2009，JPO＆INPIT

28. 发明专利

JP2008172018A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008172018A
公开(公告)日：2008-07-24
申请号：JP2007003701
申请日：2007-01-11
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAITO MASAYOSHI
IPC分类号： H01L21/768 , C23C14/34 , H01L21/304 , H01L21/3205
CPC分类号： H01L23/53223 , H01L21/2855 , H01L21/76804 , H01L21/76843 , H01L21/76844 , H01L21/7685 , H01L21/76858 , H01L21/76877 , H01L21/76882 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method for simultaneously depositing and forming an AlCu plug filling a connection hole and an AlCu wiring formed on an interlayer insulating film. SOLUTION: AlCu is simultaneously deposited in a connection hole 17 and on the surface of an interlayer insulating film 16 so as to form an AlCu film 20. The surface of the AlCu film 20 is polished with CMP so as to form a TiN anti-reflective film 21 thereonto. The TiN anti-reflective film 21 having the flat surface is formed in order to prevent the occurrence of halation during the patterning of a layered wiring including the AlCu film 20, and also, to prevent penetration of an etchant during the wet etching. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种用于同时沉积和形成填充连接孔的AlCu插头和形成在层间绝缘膜上的AlCu布线的半导体器件制造方法。解决方案：AlCu同时沉积在连接孔17中和层间绝缘膜16的表面上以形成AlCu膜20.AlCu膜20的表面用CMP抛光以形成TiN 抗反射膜21。形成具有平坦表面的TiN抗反射膜21，以防止在包括AlCu膜20的层状布线的图案化期间发生晕影，并且还防止在湿蚀刻期间蚀刻剂的穿透。版权所有（C）2008，JPO＆INPIT

29. 发明专利

JP2008153609A Method for forming metal wiring of semiconductor device 有权
标题翻译：形成半导体器件金属接线的方法
公开(公告)号：JP2008153609A
公开(公告)日：2008-07-03
申请号：JP2007135580
申请日：2007-05-22
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： HONG SEUNG HEE , JEONG CHEOL MO , KIM JUNG GEUN , KIN ONSHIYU
IPC分类号： H01L21/3205
CPC分类号： H01L21/28562 , H01L21/32131 , H01L21/76879 , H01L21/76882
摘要： PROBLEM TO BE SOLVED: To provide a method for forming metal wiring of a semiconductor element that selectively vapor-deposits a metal layer having low specific resistance and flattens it after heat treatment by applying chemical vapor deposition only to an upper part of a barrier metal layer inside a trench, thereby being able to form a low specific resistance metal wiring. SOLUTION: Using RF etching method, a barrier metal layer 120 is left only on a bottom face of a trench 108 and on a lower sidewall of an insulating film pattern. Using CVD method that employs an MPA source as a precursor, a metal layer 130 having low specific resistance is selectively vapor-deposited only on an upper part of the barrier metal layer 120, and is flattened to form a metal wiring 140 after heat treatment is carried out. The heat treatment conducts flattening by completely filling the trench 108 with a metal material. This way, dishing and scratching that may be caused by brittle aluminum do not occur and high reliability as the metal wiring 140 can be secured to produce the metal wiring having low specific resistance. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成半导体元件的金属布线的方法，其选择性地将具有低电阻率的金属层蒸发沉积，并且在热处理之后使其化学气相沉积仅在其上部阻挡金属层，从而能够形成低电阻金属布线。解决方案：使用RF蚀刻方法，阻挡金属层120仅留在沟槽108的底面和绝缘膜图案的下侧壁上。使用MPA源作为前体的CVD方法，仅在阻挡金属层120的上部选择性地气相沉积具有低电阻率的金属层130，并且在热处理后被平坦化以形成金属布线140 执行。热处理通过用金属材料完全填充沟槽108来进行扁平化。这样，不会发生由脆性铝引起的凹陷和刮伤，并且可以确保金属布线140的高可靠性，以制造具有低电阻率的金属布线。版权所有（C）2008，JPO＆INPIT

30. 发明专利

JP3963494B2 Semiconductor device and method of forming the same 失效
公开(公告)号：JP3963494B2
公开(公告)日：2007-08-22
申请号：JP16832995
申请日：1995-06-09
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：相忍李 , 善鎬河
IPC分类号： H01L21/28 , H01L21/768 , H01L21/285 , H01L23/522
CPC分类号： H01L21/76876 , H01L21/28518 , H01L21/76838 , H01L21/76843 , H01L21/76855 , H01L21/76862 , H01L21/76865 , H01L21/76882 , Y10S257/915

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