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21. 发明专利

JP4815326B2 Timing failure improving apparatus of the integrated circuit, as well as timing failure diagnostic apparatus and method for an integrated circuit, and an integrated circuit 有权
公开(公告)号：JP4815326B2
公开(公告)日：2011-11-16
申请号：JP2006295943
申请日：2006-10-31
申请人：富士通株式会社
发明人：禎彦薩川
IPC分类号： G01R31/28 , G01R31/3183 , H01L21/822 , H01L27/04
CPC分类号： G06F11/27 , G01R31/318552 , G01R31/318566 , G01R31/318594

22. 发明专利

JP2010145175A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2010145175A
公开(公告)日：2010-07-01
申请号：JP2008321209
申请日：2008-12-17
申请人： Sharp Corp , シャープ株式会社
发明人： HASHIMOTO YOSHINORI
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04
CPC分类号： H04L25/0264 , G01R31/3172 , G06F1/22 , G06F11/27 , H01L2924/0002 , H03M1/785 , H03M1/808 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To achieve a semiconductor integrated circuit suitable for microfabrication.
SOLUTION: The semiconductor integrated circuit 10 includes a digital-analogue conversion circuit 6. When signals for testing are inputted to respective input terminals 5A to 5D via respective signal lines Sig0T to Sig3T, the digital-analogue conversion circuit 6 converts digital signals of the signals for testing to an analogue signal so as to output it to a signal line So via an output terminal 7. The analogue signal passing through the signal line So is outputted to the outside from an external output terminal 4.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：实现适合于微细加工的半导体集成电路。解决方案：半导体集成电路10包括数模转换电路6.当通过各信号线Sig0T至Sig3T向各输入端子5A至5D输入测试信号时，数模转换电路6将数字信号用于测试的信号到模拟信号，以便经由输出端子7将其输出到信号线So。通过信号线So的模拟信号从外部输出端子4输出到外部。（C）2010，JPO＆INPIT

23. 发明专利

JP2010049686A Observing internal link via second link 有权
标题翻译：通过第二个链接观察内部链接
公开(公告)号：JP2010049686A
公开(公告)日：2010-03-04
申请号：JP2009183652
申请日：2009-08-06
申请人： Intel Corp , インテル・コーポレーション
发明人： ISLAM SYED , MITCHELL JAMES
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F11/27 , H01L25/065 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a hardware implementation to be integrated in a silicon component to deliver visibility using an existing external interface from an MCP, e.g., via other interconnect.
SOLUTION: Included is a step for selecting first data received in a first die of a multi-chip package (MCP) from a second die of the MCP via an intra-package link for output from a selector during a first clock period of a first clock signal, a step for selecting second data transmitted from the second die to the first die for output from the selector during a second clock period, and a step for transmitting the first and second data from the MCP via an external link.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供要集成在硅组件中的硬件实现，以使用来自MCP的现有外部接口（例如经由其他互连）提供可见性。包括的步骤是用于从MCP的第二管芯经由内部封装链路选择在多芯片封装（MCP）的第一管芯中接收的第一数据以在第一时钟周期期间从选择器输出的步骤第一时钟信号的步骤，用于选择从第二管芯发送到第一管芯以在第二时钟周期期间从选择器输出的第二数据的步骤，以及用于经由外部链路从MCP发送第一和第二数据的步骤。版权所有（C）2010，JPO＆INPIT

24. 发明专利

JP2005050329A Dependable microcontroller, method for detecting fault in microcontroller, method for designing fault permission system for dependable microcontroller, and computer program product therefor 有权
标题翻译：微控制器的检测方法，微控制器故障识别系统的设计方法及计算机程序产品
公开(公告)号：JP2005050329A
公开(公告)日：2005-02-24
申请号：JP2004204737
申请日：2004-07-12
申请人： Yogitech Spa , ヨジテック・ソシエタ・ペル・アチオニYOGITECH Spa
发明人： MARIANI RICCARDO , MOTTO SILVANO , CHIAVACCI MONIA
IPC分类号： G06F11/18 , G06F11/00 , G06F11/22 , G06F11/267 , G06F11/27 , G06F11/30 , G06F15/78
CPC分类号： G06F11/27 , Y02T10/82
摘要： PROBLEM TO BE SOLVED: To obtain perfect reliability by optimizing computer resources and a circuit size. SOLUTION: This dependable microcontroller comprises a central processing unit (50, 51) and a further fault processing unit (11) suitable for performing the validation of the operation of the central processing unit (50, 51). The further fault processing unit (11) is externally located and different with respect to the central processing unit (51). The further fault processing unit (11) comprises at least a module for performing the validation of the operation of the central processing unit and one or more modules suitable for performing the validation of operations of other functional parts of the microcontroller (10). COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过优化计算机资源和电路大小来获得完美的可靠性。解决方案：该可靠的微控制器包括适于执行中央处理单元（50,51）的操作的验证的中央处理单元（50,51）和另外的故障处理单元（11）。另外的故障处理单元（11）相对于中央处理单元（51）位于外部并且不同。所述另外的故障处理单元（11）至少包括用于执行中央处理单元的操作的验证的模块和适于执行微控制器（10）的其他功能部件的操作的验证的一个或多个模块。版权所有（C）2005，JPO＆NCIPI

25. 发明专利

JP2004301856A Scanning method 3 weight-added random scan built-in self-test circuit 有权
标题翻译：扫描方式3加权随机扫描内置自检电路
公开(公告)号：JP2004301856A
公开(公告)日：2004-10-28
申请号：JP2004183137
申请日：2004-06-21
申请人： Nec Corp , 日本電気株式会社
发明人： SONMUN WAN
IPC分类号： G01R31/28 , G01R31/3181 , G01R31/3183 , G01R31/3185 , G06F11/22 , G06F11/263 , G06F11/27
CPC分类号： G06F11/27 , G01R31/31813 , G01R31/318547 , G06F11/263
摘要： PROBLEM TO BE SOLVED: To provide a scanning method 3 weight-added random scan built-in self-test circuit for reducing test sequence length and hardware overhead in 3 weight WRPT BIST (test-per-clock and scanning method). SOLUTION: This scanning method built-in self-test circuit is to produce a test set for sensing any failure hard to be detected. It identifies a set of failures hard to detect, and then uses an advanced automatic test pattern generator to produce the test set for sensing any failure hard to be detected. In this case, it applies the advanced automatic test pattern generator so as to allow for both hardware overhead and test sequence length, while making the hardware overhead to be generated when a new test cube is added to the test set. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种扫描方式3重量随机扫描内置自检电路，用于减少3个重量WRPT BIST（每个时钟和扫描方法）中的测试序列长度和硬件开销。
解决方案：这种内置自检电路的扫描方法是产生一个测试装置，用于感测难以检测的任何故障。它识别出一组难以检测的故障，然后使用高级自动测试模式发生器来产生用于感测难以检测到的任何故障的测试集。在这种情况下，它应用高级自动测试模式生成器，以便允许硬件开销和测试序列长度，同时在将新的测试多维数据集添加到测试集中时产生硬件开销。版权所有（C）2005，JPO＆NCIPI

26. 发明专利

JPS5917644A Self-diagnozing method of microprocessor system 失效
标题翻译：微处理器系统的自我诊断方法
公开(公告)号：JPS5917644A
公开(公告)日：1984-01-28
申请号：JP12699382
申请日：1982-07-21
申请人： Yokogawa Hokushin Electric Corp
发明人： TAKIGISHI SHINICHI , KOBAYASHI MITSURU , SANO HIDEO
IPC分类号： G06F11/22 , G06F11/27
CPC分类号： G06F11/27
摘要： PURPOSE:To detect the fault of a microprocessor system under the status that the normal function is being executed, by providing a program to detect the fault of the processor and a memory to a part of a task. CONSTITUTION:Diagnozing data are previously stored in a fixed address to check the fixed address of the memory and the operation of the processor. At first, the contents #5555 of the address A1 stored in the 1st location of a register, data #AAAA of the succeeding address of A1, and then #FFFF are inputted to the processor. If it is defined that the contents of the address A1 is (A1), the contents of the succeeding address is (A1+1) and the contents of the 3rd address is (A1+2), the processor executes (A1)+(A1+1) & (A1+2)+1=0. After the address A2, the processor executes A2 X A3 divided by A4=A5 residual A6. When said formulas are not satisfied, whether the reading operation of the contents of the fixed address or the operation of the processor is defective.
摘要翻译：目的：通过提供一个程序来检测处理器的故障和一个任务的一部分内存，来检测微处理器系统在正常功能正在执行的状态下的故障。规定：诊断数据先前存储在固定地址中，以检查存储器的固定地址和处理器的操作。首先，将存储在寄存器的第一位置的地址A1的内容#5555，A1的后续地址的数据#AAAA，然后#FFFF输入到处理器。如果定义地址A1的内容为（A1），则后续地址的内容为（A1 + 1），第3地址的内容为（A1 + 2），处理器执行（A1）+（ A1 + 1）＆（A1 + 2）+ 1 = 0。在地址A2之后，处理器执行A2×A3除以A4 = A5残差A6。当不满足所述公式时，固定地址的内容的读取操作或处理器的操作是否有缺陷。

27. 发明专利

JPS58200352A Diagnostic system of arithmetic option hardware 失效
标题翻译：算术选择硬件诊断系统
公开(公告)号：JPS58200352A
公开(公告)日：1983-11-21
申请号：JP8267782
申请日：1982-05-17
申请人： Toshiba Corp
发明人： YAMAGUCHI TAKAYUKI
IPC分类号： G06F7/00 , G06F9/38 , G06F11/22 , G06F11/27
CPC分类号： G06F11/27
摘要： PURPOSE:To eliminate the need for a special interface signal and an additional circuit, by utilizing the combination of condition codes which never happens in normal arithmetic as option diagnostic error information. CONSTITUTION:A selecting circuit 125 is positioned between an interface driver 124, and a condition code flag 122 and an error flag 123. Then, it receives information from each flag and selects output information to be transmitted to the condition driver on an interface according to whether an error occurs or not. If option hardware 12 detects an error occurring to the result of a self-diagnosis in a free time, the flag 123 is set to a code for the error. Consequently, a CPU11 when using the hardware 12 checks whether the condition code is the error code or not to confirm the faulted state of the hardware 12.
摘要翻译：目的：为了消除对特殊接口信号和附加电路的需要，通过利用常规算术中从不发生的条件代码的组合作为选项诊断错误信息。构成：选择电路125位于接口驱动器124和条件代码标志122和错误标志123之间。然后，它从每个标志接收信息，并根据接口驱动器选择要发送到接口上的状态驱动器的输出信息是否发生错误。如果选项硬件12在空闲时间内检测到自诊断结果发生错误，则标志123被设置为用于该错误的代码。因此，当使用硬件12时，CPU11检查条件代码是否是错误代码，以确认硬件12的故障状态。

28. 发明专利

JPS5769349A Lsi circuit chip inspecting device 失效
标题翻译： LSI电路芯片检查设备
公开(公告)号：JPS5769349A
公开(公告)日：1982-04-28
申请号：JP10617381
申请日：1981-07-07
申请人： Control Data Corp
发明人： NIKORASU PURATSUTO BAN BURUNTO
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G06F11/22 , G06F11/27
CPC分类号： G01R31/318536 , G06F11/27

29. 发明专利

JPS5752950A Digital signal processor 失效
标题翻译：数字信号处理器
公开(公告)号：JPS5752950A
公开(公告)日：1982-03-29
申请号：JP11238181
申请日：1981-07-20
申请人： Philips Nv
发明人： MARINUSU TEODORUSU MARIA SEEGA , KORUNERISU NIISEN , KURIIN KUITSUPERU
IPC分类号： G01R31/28 , G01R31/3183 , G06F11/22 , G06F11/27
CPC分类号： G06F11/27

30. 发明专利

JP6438353B2 半導体装置及び診断テスト方法审中-公开
公开(公告)号：JP6438353B2
公开(公告)日：2018-12-12
申请号：JP2015107472
申请日：2015-05-27
申请人：ルネサスエレクトロニクス株式会社
发明人：芝原真一 , 川上大輔 , 井学豊
IPC分类号： G06F11/267 , G01R31/28 , G06F11/22
CPC分类号： G01R31/3177 , G01R31/31724 , G06F11/27

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