专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明专利

JPS56124950A DATA PROCESSING EQUIPMENT 失效
公开(公告)号：JPS56124950A
公开(公告)日：1981-09-30
申请号：JP2654980
申请日：1980-03-05
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , IKEDA KOUICHI
IPC分类号： G06F9/22
摘要： PURPOSE:To elevate the reliability and workbility of an equipment, by suppressing the subsequent execution by a hardware means, when the contents of a fundamental area and a control register have been rewritten by mistake, by executing a microprogram which has been prepared by a user. CONSTITUTION:1 word of a microprogram which has been read out from the control memory device 1 is set to the fields F1-F3 of the contol register 4. Also, the device is made a fundamental area and a firmware area, and a specific microinstruction by which the contents of the fundamental area used in the firmware, and the register 4, etc. are rewritten by mistake is defined as a privilege microinstruction. And, the privilege microinstruction of each field F1-F3 is discriminated by the microinstruction discriminating circuits 6-8, and an output signal S4 is made ''1'' and is output from the OR gate 9. Also, an output signal S0 of the firmware area, which has been discriminated by the address discriminating circuit 5 is provided to the AND gate 10 together with the signal S4, and when there is a privilege microinstruction, it is suppressed to execute the subsequent instruction by the microinstruction execution suppressing circuit 11.

22. 发明专利

JP2001222885A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001222885A
公开(公告)日：2001-08-17
申请号：JP2000032636
申请日：2000-02-03
申请人： HITACHI LTD
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KOBAYASHI TORU , MIYAOKA SHUICHI , YOKOYAMA YUJI , SAWAMOTO HIDEO , KUME SHOJI
IPC分类号： G06F12/08 , G11C7/10 , G11C11/401 , G11C11/4093
摘要： PROBLEM TO BE SOLVED: To improve the throughput of external output operation of read data for a memory block capable of performing parallel operation. SOLUTION: This circuit is provided with read buffers RB0-RB3 which can hold the read data read out from plural memory blocks BNK0-BNK7 capable of performing the parallel operation corresponding to a state that the read data can not be outputted from an external interface means to the outside, and selecting means 40, 41 and 42 which select the read data read out from the read buffer and give the read data to an external interface means when the state that the read data can not be outputted is eliminated. Thus, when there is the possibility of conflict of resources in the output operation of the read data, the read data is stored in the read buffer, and when there is no possibility, the read data can be outputted directly to the outside, thereby improving the throughput of output operation of the read data.

23. 发明专利

JPH06259322A CACHE MEMORY SYSTEM 失效
公开(公告)号：JPH06259322A
公开(公告)日：1994-09-16
申请号：JP4142493
申请日：1993-03-02
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： TAKADA MITSUO , SAWAMOTO HIDEO , KOBAYASHI TAKAO , HORIUCHI HIROO , MORIOKA MICHIO
IPC分类号： G06F12/08
摘要： PURPOSE:To secure the identity between duplicate data registered in an instruction cache memory and a data cache memory without fail, and to evade unnecessary data registration processing from a main memory and improve the throughput of the cache memory system which has the instruction cache memory and data cache memory. CONSTITUTION:The throughput of a processor is improved by guaranteeing the identity of common data even in operation other than a data fetch by providing a common data discrimination information controller 140 which re-sets a common bit (common data discrimination information) indicating whether or not the same instruction code with data registered in the data cache memory 110 is registered in the instruction cache memory 110 according to five kind of discrimination signals (2001-2005) outputted by cache data discriminating devices 120 and 130 for instructions and data of the instruction and data cache memories 100 and 110.

24. 发明专利

JPH0492929A INFORMATION PROCESSOR 失效
公开(公告)号：JPH0492929A
公开(公告)日：1992-03-25
申请号：JP20688890
申请日：1990-08-06
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO
IPC分类号： G06F9/455
摘要： PURPOSE:To support both architectures At by switching At mode bits designating by which one of the two architectures At consisting of instruction sets different in instruction specifications a system is operated. CONSTITUTION:The bits 1-19 of a control register CR1 are STO, and bits 25-31 are STL and they are defined by the architecture At I. Bits 20-24 are extension/ degeneration mode bits X and D, extension/degeneration instruction monitor indicators XM and DM and a special degeneration mode bit S. The instruction sets A, DI, DII and E are executed by a processing flow in the figure in accor dance with said bits. When X=0, it is an instruction exception in At II. When X=1, the instruction processing of a definition A is executed in At I. DI and DII are the same operand codes but they are the instruction sets different in the processings in At I and II. The instruction processing of DI is executed in D=1, and that of DII in D=0. In the operand code of E, it is the instruction exception in At II and the processing of the instruction of DII is executed in S=1. Thus, shift to At without partial compatibility is facilitated.

25. 发明专利

JPH03190159A SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH LOGIC 失效
公开(公告)号：JPH03190159A
公开(公告)日：1991-08-20
申请号：JP32919289
申请日：1989-12-19
申请人： HITACHI LTD
发明人： MIYAOKA SHUICHI , ODAKA MASANORI , SAWAMOTO HIDEO , KATO MASAO , SUMIMOTO TSUTOMU
IPC分类号： H01L27/118 , G11C11/401 , H01L21/82 , H01L27/10
摘要： PURPOSE:To enable the formation of a memory of large capacity and a large scale logic on the same chip without decreasing it in operation speed and increasing it in power consumption by a method where a memory section is formed of a CMOS memory cell or a high resistance load type NMOS memory cell, and a gate array section is formed of a Bi-CMOS logic gate composed of a bipolar transistor and a CMOS circuit. CONSTITUTION:An input latch circuit 24 out of the circuits of a memory section is formed of a CMOS circuit to be decreased in power consumption, and an X decoder 22, a Y decoder 23, and a sense amplifier & output circuit 25 are formed of a Bi-CMOS circuit to be lessened in power consumption and improved in operation speed. Readout data are inputted into a gate array section through the intermediary of an aligner circuit 27. The aligner circuit 27 is given as a dedicated logic circuit designed using a Bi-CMOS gate so as to lessen a semiconductor memory device in area keeping it high operation speed. As a clock amplifier 28 can be used in common for memory mats vertically adjacent to each other, two pairs of vertically arranged memory mats are symmetrically laid out, and the aligner circuit 27 and a clock amplifier 28 are arranged at a position shown by a dot-dash line A.

26. 发明专利

JPS6428758A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6428758A
公开(公告)日：1989-01-31
申请号：JP18332287
申请日：1987-07-24
申请人： HITACHI LTD
发明人： ARA MARI , SAWAMOTO HIDEO , YAMAGATA MAKOTO
IPC分类号： G06F9/46 , G06F12/10
摘要： PURPOSE:To invalidate a buffer at high speed by rewriting the identifier register of a processor to a new identifier for every invalidating processing of an address converting buffer and converting the address thereafter by the use of the address converting buffer holding the new identifier. CONSTITUTION:At the time of making access to the address converting buffer of a virtual computer, the relevant entry of the buffer 2 is made access by the use of a part of the virtual address of a logical address register 3 to compare in a comparison circuit 5 whether the virtual address part (L) read therefrom coincides with the high order address part of the register 3 or not. In the identifier VMID in the buffer 2, an identifying information value at the time of registering an entry is stored to compare in a comparison circuit 4 whether the read identifier VMID coincides with a currently travelling identification number or not. Thereafter, when the two inputs of the circuits 4, 5 coincide, an output is fed to an AND gate 6 to establish an AND condition and output a real address for a real computer to the buffer 2.

27. 发明专利

JPS6412351A VIRTUAL STORAGE CONTROL SYSTEM 失效
公开(公告)号：JPS6412351A
公开(公告)日：1989-01-17
申请号：JP16843987
申请日：1987-07-06
申请人： HITACHI LTD
发明人： TANIGUCHI TOSHIHISA , SAWAMOTO HIDEO
IPC分类号： G06F12/12
摘要： PURPOSE:To prevent the overhead of an operating system from being increased, by providing a reference counter of (n) bits which holds the number of times of page reference at every prescribed period in a unit of page instead of the reference bit of a main storage key. CONSTITUTION:An RC array 102 of (n) bits is counted up at an adder circuit 105 at every reference of the said page. When all bits are set at (1)s, no count-up is performed. And the operating system issues an instruction (RRC instruction) to read out the value of an RC (reference counter) within the prescribed period, and reads out the value of the said page of the RC array 102, and updates a nonreference time interval counter according to a count value, and rearranges the queue of the page targeted to be paged out. At this time, the said RC is reset.

28. 发明专利

JPS6353574B2 失效
公开(公告)号：JPS6353574B2
公开(公告)日：1988-10-24
申请号：JP16494883
申请日：1983-09-09
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , YAMADA TAKAFUMI
IPC分类号： G06F9/46 , G06F12/10

29. 发明专利

JPS63228352A STORAGE PROTECTION SYSTEM FOR VIRTUAL COMPUTER SYSTEM 失效
公开(公告)号：JPS63228352A
公开(公告)日：1988-09-22
申请号：JP6101387
申请日：1987-03-18
申请人： HITACHI LTD
发明人： SAWAMOTO HIDEO , UMENO HIDENORI
IPC分类号： G06F12/10 , G06F9/46 , G06F12/14
摘要： PURPOSE:To set the occurrence of the protection exception of a virtual computer same as that in the case which a program is executed in a real computer by generating the interruption of the protection exception in the virtual computer or a guest computer if storage protection information is detected when a TLB is collated. CONSTITUTION:If storage protection information is detected when the address conversion buffer (TLB) is collated, the interruption of the storage protection exception is generated in the virtual computer or the host computer corresponding to the storage protection information. Thus, the storage protection of the host and the quest can be discriminated and detected, and the storage protection exception by the guest can interrupt in the guest and that by the host in the host, whereby a program which runs in the guest is interrupted similarly to the case in which the program is executed in the real computer. Thus, the difference with the execution in the real computer is eliminated and the original action of the virtual computer can be executed.

30. 发明专利

JPS60229162A CONTROL SYSTEM OF MULTIPROCESSOR 失效
公开(公告)号：JPS60229162A
公开(公告)日：1985-11-14
申请号：JP8371984
申请日：1984-04-27
申请人： HITACHI LTD
发明人： IMAI KANAME , SAWAMOTO HIDEO
IPC分类号： G06F12/00 , G06F13/38 , G06F15/16 , G06F15/167 , G06F15/177
摘要： PURPOSE:To attain easy control with less hardware by setting an exclusive memory for hardware on a main storage device and transmitting/receiving commands or information related to the commands between respective processors through said memory. CONSTITUTION:When a processing request is sent from a processor (CPU)2 to a CPU3, the CPU2 stores a processing request command for the CPU3 and its accompanied information in the exclusive memory 10 for the hardware which is arranged in the main storage device (MS)4 through a signal line 100 and then informs the existence of the processing request to the CPU3 through a signal line 500. On the basis of the request, the CPU3 reads out the contents of the memory 10 in the MS4 through a signal line 300 at the division of the processing to generate the request. The corresponding data is transmitted to the CPU3 through a signal line 400.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式