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21. 发明专利

JP2004038806A Address translation device and method and double hierarchy address translation device 有权
标题翻译：地址翻译设备和方法以及双层级地址翻译设备
公开(公告)号：JP2004038806A
公开(公告)日：2004-02-05
申请号：JP2002197952
申请日：2002-07-05
申请人： Fujitsu Ltd , 富士通株式会社
发明人： CHIBA TAKUMA , HONKURUMADA TSUTOMU , YAMAZAKI IWAO
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681
摘要： PROBLEM TO BE SOLVED: To provide an address translation device, an address translation method, and a double hierarchy address translation device for translating an address at a high speed. SOLUTION: This address translation device is provided with a TLB 161 and a selection signal generation circuit 110. In the TLB 161, OP-TLB 161a storing operand TLB data for translating OP-ACS-ADD-VA (operand virtual address) into a physical address PA and IF-TLB 161b storing instruction TLB data for translating IF-ACS-ADD-VA (instruction virtual address) into the physical address PA share the same TLB-RAM 160. The selection signal generation circuit 110 generates a signal, by which operand access is carried out by priority when an access collision occurs between the operand access and instruction access, the IF-ACS-ADD-VA is held in a waiting register 190, and after the operand access is finished, the instruction access is operated on the basis of Wait-IF-VA (waiting instruction virtual address). COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供用于高速地翻译地址的地址转换装置，地址转换方法和双层地址转换装置。解决方案：该地址转换装置具有TLB 161和选择信号生成电路110.在TLB 161中，存储用于转换OP-ACS-ADD-VA（操作数虚拟地址）的操作数TLB数据的OP-TLB 161a，存储用于将IF-ACS-ADD-VA（指令虚拟地址）转换为物理地址PA的指令TLB数据的物理地址PA和IF-TLB 161b共享相同的TLB-RAM 160.选择信号生成电路110生成信号当在操作数访问和指令访问之间发生访问冲突时优先执行操作数访问，IF-ACS-ADD-VA被保持在等待寄存器190中，并且在操作数访问完成之后，指令访问基于Wait-IF-VA（等待指令虚拟地址）操作。版权所有（C）2004，JPO

22. 发明专利

JPH07295883A INFORMATION PROCESSOR 失效
公开(公告)号：JPH07295883A
公开(公告)日：1995-11-10
申请号：JP9189594
申请日：1994-04-28
申请人： FUJITSU LTD
发明人： YAMAZAKI IWAO , HIROSE MOTOYOSHI , MORI TSUYOSHI , OKADA MASAYUKI
IPC分类号： G06F12/16 , G06F12/08
摘要： PURPOSE:To suppress the wasteful increase of a memory resource so that the restoration processing of an error is executed in a shortest time in accordance with an error state, and simultaneously, to simplify error processing procedure so that the management of data is facilitated as well in respect of an information processor constituted so that caches are provided hierarchically between the processor and a storage device. CONSTITUTION:This information processor is constituted so that each cache 3 is provided with a first informing means 8 to inform another hierarchy of the entry address of an error occurring part or an error detection fact at the time of the detection of the error, a retrieving means 9 to search a tag copying part 6 by the entry address and fetch the address and the status of that data at the time when the error detection fact is informed, a second informing means 10 to inform the higher order hierarchy of the invalidating request, etc., of the error occurring part together with the address of the above-mentioned data on the basis of that status, and a processing executing means 11 to execute the processing of the invalidation, etc., of the corresponding data at the time of the information of the invalidating request, etc., from the lower order hierarchy.

23. 发明专利

JP2003131948A METHOD AND DEVICE FOR CONTROLLING CACHE 审中-公开
公开(公告)号：JP2003131948A
公开(公告)日：2003-05-09
申请号：JP2001328022
申请日：2001-10-25
申请人： FUJITSU LTD
发明人： KIMURA HIROAKI , SHIROHIGE YUJI , YAMAZAKI IWAO
IPC分类号： G06F12/08 , G06F12/10 , G06F12/14
摘要： PROBLEM TO BE SOLVED: To provide an information processing system provided with a cache memory device and key control protection for a main memory device with a main memory key, which can increase in data access efficiency. SOLUTION: An information processing system executes a request process for a main memory key following an address conversion process by DAT if a TLB miss is caused by an access request for the main memory. A result of the conversion is registered in the TLB and the request process for the main memory is restarted while the information processing system is waiting for the arrival of the main memory key being requested. If the request process for the main memory hits the TLB, then, corresponding data is send out. The processing system afterward checks the legitimacy of the access by using the main memory key arrived and sends a report for process completion.

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