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21. 发明专利

JPH0340515A DECISION FEEDBACK TYPE EQUALIZER 失效
公开(公告)号：JPH0340515A
公开(公告)日：1991-02-21
申请号：JP17484589
申请日：1989-07-06
申请人： FUJITSU LTD
发明人： AWATA YUTAKA , KAWADA KINJI , KUGIMIYA JUNICHI , FUKUDA SETSU
IPC分类号： H03H21/00 , H04B3/04
摘要： PURPOSE:To accurately update tap factors by allowing an adaptive filter part to execute the adaptive control of a weight factor based upon a decision value of a decider and an error of a 2nd synthesizer for finding out an error between the equalizing outputs of a 1st synthesizer. CONSTITUTION:The decision feedback type equalizer is provided with an adaptive transversal filter part 1, a subtractor 2, the decider 3, a subtractor 4, and a multiplier 5. The multiplier 5 is constituted to multiply the decision value (ak) by a correction factor K and input the corrected value K.ak to the subtractor 4 as a subtraction value. An accurate error (ek) based upon inter-code interference can be obtained by subtracting the output of the multiplier 5 from the output (dk) of the equalizer. Consequently, the tap factors C1 to Cn can be accurately updated.

22. 发明专利

JPH1188152A DIGITAL PLL CIRCUIT 失效
公开(公告)号：JPH1188152A
公开(公告)日：1999-03-30
申请号：JP24250697
申请日：1997-09-08
申请人： FUJITSU LTD
发明人： KUGIMIYA JUNICHI , HIROME MASASHI , NARITA KENJI
IPC分类号： H03L7/06
摘要： PROBLEM TO BE SOLVED: To weaken the connection of a reference input signal with the output of VCO and to suppress the jitter component of comparatively quick change by permitting a phase deviation for the portion of one cycle against the output of a voltage control oscillator(VCO). SOLUTION: A period with the rise of the reference input signal (the one where the phases coincides and a comparison result by a comparator 4 is a same value) is measured by a reference input signal cycle or the output signal cycle of VCO 1 in a phase detecting window for the portion of one cycle of the output signal in VCO 1. The absolute value of controlled variable for controlling VCO 1 is stored in a referring table or obtained by calculation. The controlled variable is accumulated with preceding controlled variable by an accumulator constituted by having a full addition arithmetic equipment 10 with a clip function and its result is inputted to VCO 1 as the control voltage of VCO 1. A digital/analog converter(DAC) 2 is used as a means for executing conversion into the control voltage of VCO 1.

23. 发明专利

JPH06311073A ECHO CANCELLER 失效
公开(公告)号：JPH06311073A
公开(公告)日：1994-11-04
申请号：JP9169993
申请日：1993-04-20
申请人： FUJITSU LTD
发明人： TANAKA TAKESHI , KUGIMIYA JUNICHI , TOMITA YOSHIHIRO
IPC分类号： H04B3/23
摘要： PURPOSE:To provide an echo canceller capable of sending/receiving a voice signal, a FAX signal and a personal computer signal without hindrance when a G3 standard FAX signal and a personal computer signal using a high speed M0DEM are sent through a telephone line having the echo canceller. CONSTITUTION:The echo canceller is provided with an echo canceller control section 8 having a training signal detection means 5 stopping a function of an echo canceller section 4 when a MODEM training signal is detected by a sender side or a receiver side of a 4-wire line 2 and having a silence detection means 6 releasing the operation stop of the echo canceller section 4 when the means 6 detects silence consecutively for a time (nearly 4 sec) till an exchange terminates the call processing and accepts a succeeding call from the sender side and the receiver side of the 4-wire line 2.

24. 发明专利

JPH0635698A REPEAT INSTRUCTION WITH CONDITION EXECUTION CONTROL SYSTEM 失效
公开(公告)号：JPH0635698A
公开(公告)日：1994-02-10
申请号：JP19049792
申请日：1992-07-17
申请人： FUJITSU LTD
发明人： UTSUGI KIYOSHI , KURIHARA HIDEAKI , SAKAMOTO KEIZO , KUGIMIYA JUNICHI , OBARA HIROSHI
IPC分类号： G06F7/00 , G06F5/01 , G06F7/76 , G06F9/32
摘要： PURPOSE:To execute a normalizing processing in a fixed point arithmetic operation only by a repeat instruction in a simple constitution, in a repeat instruction execution control system with a condition in which the repeat instruction can be efficiently executed. CONSTITUTION:This system is equipped with an arithmetic part 1 and a program control part 2, the program control part 2 is equipped with a repeat counter 3, and the same arithmetic processing in the number of times set in the repeat counter 3 according to the repeat instruction is executed by the arithmetic part 1. And also, the system is equipped with a status register 4 and a logic circuit 6. Then, the most significant code bit and the second bit from the most significant one of a register 5 which sets the output of the arithmetic part 1 are inputted to the logic circuit 6, a flag is set in the status register 4 when those bits are oppositely '1' and '0', and when the flag is set regardless of the content of the repeat counter 3, the execution of the repeat instruction is ended.

25. 发明专利

JPH03190335A TIMING RECOVERY CIRCUIT 失效
公开(公告)号：JPH03190335A
公开(公告)日：1991-08-20
申请号：JP32828689
申请日：1989-12-20
申请人： FUJITSU LTD
发明人： KUGIMIYA JUNICHI , AWATA YUTAKA , FUKUDA SETSU
IPC分类号： H04L7/00 , H04L7/027
摘要： PURPOSE:To decide an optimum phase in a short time even from a reception signal waveform in which inter-code interference by a future signal exists timewise by deciding a sample timing lead from a sample timing supplying the maximum value of a smoothed impulse response string as the optimum timing phase of the reception signal. CONSTITUTION:An impulse response string subjected to the effect of inter-code interference is smoothed at first by a low pass filter means 8 to correct the difference due to the effect of the inter-code interference. Then a maximum phase decision means 9 decides a sample timing being a sample timing supplying an impulse response resulting from multiplying a prescribed number smaller than the unity with the maximum value of a smoothed impulse response string and led from the sample timing supplying the maximum value of the smoothed impulse response string as the optimum timing phase of a reception signal. Thus, the optimum phase is decided in a short time even from a reception signal waveform in which inter-code interference by a future signal exists timewise.

26. 发明专利

JPH0394539A TIMING RECOVERY CIRCUIT 失效
公开(公告)号：JPH0394539A
公开(公告)日：1991-04-19
申请号：JP23118689
申请日：1989-09-06
申请人： FUJITSU LTD
发明人： AWATA YUTAKA , OTA SHINJI , KUGIMIYA JUNICHI , MIYOSHI SEIJI
IPC分类号： H04L7/02
摘要： PURPOSE:To generate a stable timing recovery clock without jitter at all times by comparing a peak of an impulse response with two threshold levels as convergence phase object values, generating a non-control signal when the peak exists between both the threshold levels and generating a phase control signal corresponding to the quantity of a difference when the value is at the outside of both the threshold levels. CONSTITUTION:A comparator 6 compares a peak value h0 of an impulse response calculated by an impulse response arithmetic section 5 with two threshold levels hth1, hth2 as convergence phase object values and generates a non- control signal when the peak value h0 is within both the threshold levels and generates a phase control signal corresponding to the quantity of the difference when the peak value h0 exists at the outside of both the threshold levels to give the result to a master clock frequency divider 7. Thus, no phase control is implemented near the convergence phase and phase control is applied only when the convergence phase is parted. Thus, optimum phase control is always realized without jitter.

27. 发明专利

JPH0338119A AUTOMATIC EQUALIZER 失效
公开(公告)号：JPH0338119A
公开(公告)日：1991-02-19
申请号：JP17321189
申请日：1989-07-05
申请人： FUJITSU LTD
发明人： KAWADA KINJI , AWATA YUTAKA , KUGIMIYA JUNICHI , OTA SHINJI
IPC分类号： H03H21/00 , H04B3/06
摘要： PURPOSE:To realize the equalizer with small sized circuit constitution with the limited number of line equalization curves by deciding an optimum gain characteristic of a f equalizing section while applying AGC to a signal of a frequency f1 and converting the characteristic into the gain characteristic expected to be optimum in the frequency f2 based on an inter-frequency line loss relation. CONSTITUTION:A reception signal R of a main frequency f1 is inputted to a f equalizing circuit 1 and line equalization is applied according to a prescribed gain characteristic. The reception signal ER subject to line equalization by the f equalizing circuit 1 is converted into a digital signal by an A/D converter 2 and inputted to a power calculation section 3. The calculated power P is fed to a gain setting section 4 and a gain code GC is revised by one when the value is not outside of an object range PUN-POV to revise the gain characteristic of the f equalizing circuit 1. The decided gain code GC is inputted to a gain code conversion section 6, from which a gain code GC' corresponding to the optimum gain characteristic is converted in the f equalizing circuit 1 when the reception signal R with a main component frequency f2 is inputted.

28. 发明专利

JPH01228203A VOLTAGE GENERATION CIRCUIT 失效
公开(公告)号：JPH01228203A
公开(公告)日：1989-09-12
申请号：JP5437588
申请日：1988-03-08
申请人： FUJITSU LTD
发明人： KUGIMIYA JUNICHI , AWATA YUTAKA , YAMATO SEIICHI , KAWADA KINJI , TOKIWA KOJI
IPC分类号： H03F3/343 , H03F3/34
摘要： PURPOSE:To selectively generate a stable voltage in spite of a load by connecting the output terminals of plural unity gain operational amplifiers to the common output terminal of an analog switch. CONSTITUTION:In a voltage generation circuit to select the output of one voltage generation source by the analog switch out of plural voltage generation sources consisting of the unity gain operational amplifiers, respectively, the output terminal of the analog switch SW is connected to the inversion input of the operational amplifier OPi (i=1-N). In other words, since the output voltage of each of the amplifiers OP1-OPN is outputted via the analog switch SW and the output voltage of the analog SN is set as the inversion input for the operational amplifiers OP-OPN, it is possible to always set the output voltage VOUT of a selected voltage generation source at a level equal to a non-inversion input voltage Vi in spite of the ON-resistance of the analog switch SW.

29. 发明专利

JPH01226238A TIMING REPRODUCTION CIRCUIT 失效
公开(公告)号：JPH01226238A
公开(公告)日：1989-09-08
申请号：JP5202088
申请日：1988-03-04
申请人： FUJITSU LTD
发明人： KAWADA KINJI , AWATA YUTAKA , TOKIWA KOJI , YAMATO SEIICHI , KUGIMIYA JUNICHI
IPC分类号： H04L7/033 , H04L7/02
摘要： PURPOSE:To always and automatically position the leading edge or trailing edge of a DPLL output in the center of an eye pattern by phase-adjusting a master clock based on the bias of the center part of a slice waveform in the eye pattern and the leading or trailing point of the DPLL circuit output. CONSTITUTION:The title circuit has a phase comparator 21 and a phase adjuster 22 which phase-adjusts the master clock in accordance with phase decision information. The phase comparator 21 inputs the slice waveform of the eye pattern outputted from a comparator 1 and the output of the phase adjuster 22 to a charge and discharge control circuit 31, and a capacitor C is charged before the leading point of the DPLL circuit 2, whereby discharge is executed after the leading point. When the leading edge of the DPLL output is in the center part of the slice waveform in the eye pattern, the charge and discharge voltage of the capacitor becomes zero, and an off set voltage remains except for said part. A comparator 32 compares the off set voltage and an earth potential and generates an off/on output, which a phase decision circuit 33 decides in the trailing edge of the eye pattern, whereby phase decision information is given to the phase adjuster 22.

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