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21. 发明专利

JPS62135887A DISPLAY CONTROLLER 失效
公开(公告)号：JPS62135887A
公开(公告)日：1987-06-18
申请号：JP27736785
申请日：1985-12-10
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G5/06 , G09G1/28

22. 发明专利

JPS6249458A MEMORY DEVICE 失效
公开(公告)号：JPS6249458A
公开(公告)日：1987-03-04
申请号：JP18742185
申请日：1985-08-28
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G11C7/00 , G06F12/00
摘要： PURPOSE:To obtain a memory device that can make an image memory and a program memory coexist by adding chip selecting function. CONSTITUTION:In a memory array 50, word is constituted by lateral combination of memories M and 1 pick cell is constituted by longitudinal combination of memories M. A chip select mask register 67 holding information that selects chip of the memory array 50 is provided in a word controlling circuit 60W. A read plane mask register 63, a read control selector 63s and a read pane gate 64 are provided as a read inhibition mask device for word direction that inhibits and masks reading of a specified memory M that exists in word direction in the memory array 50. Further, a write plane mask register 65, a write control selector 65s and a write plane gate 66 are provided as a write inhibition mask device for word direction.

23. 发明专利

JPS6249457A STORAGE UNIT 失效
公开(公告)号：JPS6249457A
公开(公告)日：1987-03-04
申请号：JP18742085
申请日：1985-08-28
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G11C7/00 , G06F12/00 , G11C11/401
摘要： PURPOSE:To obtain a multifunction storage unit by giving command function to a storage unit and realizing various modes, constitution and operation basing on the command. CONSTITUTION:The unit consists of a memory array 50, a word control circuit 60W, a bit control circuit 60B and a timing control circuit 70 that controls timing of each circuit. The word control circuit 60W is a circuit that controls a control line of word direction or face direction of the memory array 50, and the circuit exists corresponding to bit number (i) that constitutes the word. The bit control circuit 60B is a circuit that controls a control line of bit direction or pixel direction of the memory array 50, and the circuit exists corresponding to bit number (j) that constitutes the pixel A data bus and a data line are made in common by one of data bus and the address line is supplied to whole of the memory array 50.

24. 发明专利

JPS61296386A MEMORY INTERFACE 失效
公开(公告)号：JPS61296386A
公开(公告)日：1986-12-27
申请号：JP13830585
申请日：1985-06-25
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G5/36 , G06F12/00 , G06F12/06 , G06T1/60 , G09G1/02 , G09G5/39 , G11C7/00

25. 发明专利

JPS61287328A AD CONVERTING CIRCUIT 失效
公开(公告)号：JPS61287328A
公开(公告)日：1986-12-17
申请号：JP12805785
申请日：1985-06-14
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： H03M1/12
摘要： PURPOSE:To obtain an inexpensive AD conversion circuit by fluctuating periodicall the entire reference voltage, allowing an output buffer to hold a preceding output signal of a signal conversion circuit and adding an output signal of the signal conversion circuit and the preceding output signal by an adder circuit. CONSTITUTION:The AD conversion circuit 100 has the signal conversion circuit 20, a reference voltage fluctuation circuit 30, a buffer 40 and the adder circuit 50. The signal conversion circuit 20 converts an analog input signal into a digital signal of the number prescribed bits based on the reference voltage. The refrence voltage fluctuation circuit 30 fulctuates the entire reference voltage of the signal conversion circuit 20 at each sampling. The buffer 40 fetches the preceding output signal in the signal conversion circuit 20. The adder circuit 50 adds the output signal of the signal conversion circuit 20 and the output signal of the buffer 40 and outputs a signal having bits more than the number of output bits of the signal conversion circuit 20 by one bit.

26. 发明专利

JPS61213896A DISPLAY CONTROLLER 失效
公开(公告)号：JPS61213896A
公开(公告)日：1986-09-22
申请号：JP5512785
申请日：1985-03-19
申请人： ASCII CORP , NIPPON MUSICAL INSTRUMENTS MFG
发明人： ISHII TAKATOSHI , KANEKO MAKOTO
IPC分类号： G09G5/18 , G02F1/133 , G06F3/147 , G06F3/153 , G09G1/16 , G09G3/20 , G09G3/36 , G09G5/00 , G09G5/22
摘要： A display controller displays an image on either of a CRT display unit and a liquid crystal display unit (LCD) having upper and lower screens in accordance with image data stored in a memory. When a CRT display unit is driven, an address generating circuit calculates at the beginning of each horizontal scanning an address of the memory corresponding to the leftmost display position on the current horizontal scanning line in accordance with the vertical position of the horizontal scanning line and the number of display positions on a horizontal scanning line, and stores data representing the address in a first register. The data in the first register is incremented in accordance with the horizontal scanning and fed to the memory to read the image data. When the LCD is driven, the address generating circuit calculates at the beginning of each horizontal scanning two addresses of the memory corresponding respectively to the left most display positions on the current horizontal scanning lines on the upper and lower screens. In this case, the first one is obtained in accordance with the vertical position of the current horizontal scanning line on the upper screen and the number of display positions on a horizontal scanning line, while the seond one is obtained by adding the number of display positions on the upper screen to the calculated first address. Data representing these two addresses are stored in the first and second registers, which data are incremented in accordance with the horizontal scanning and fed to the memory to read the image data.

27. 发明专利

JPS61213892A DISPLAY CONTROLLER 失效
公开(公告)号：JPS61213892A
公开(公告)日：1986-09-22
申请号：JP5512885
申请日：1985-03-19
申请人： ASCII CORP , NIPPON MUSICAL INSTRUMENTS MFG
发明人： ISHII TAKATOSHI , KANEKO MAKOTO
IPC分类号： G09G5/02 , G09G5/06 , G09G5/08
摘要： A display controller can display a cursor having sufficient contour irrespective of the background color. The display controller has two cursor pattern memories from which first and second cursor patterns are read in such a timing that the first cursor pattern is displayed at a selected position on the screen and that the second cursor pattern is superimposed on the first cursor pattern. The display controller also has two registers storing therein first and second color codes corresponding respectively to the first and second cursor patterns. The color of the first cursor pattern is determined by a color code obtained by subjecting the first color code and a background color code read from a video memory to a logical multiplication, and the color of the second cursor pattern is determined by a color code obtained by subjecting the color code of the first cursor pattern and the second color code to an exclusive-OR operation. The logical operations are selectively effected in accordance with two control bits stored in a register.

28. 发明专利

JPS60249185A DISPLAY CONTROLLER 失效
公开(公告)号：JPS60249185A
公开(公告)日：1985-12-09
申请号：JP10609284
申请日：1984-05-25
申请人： ASCII CORP , NIPPON MUSICAL INSTRUMENTS MFG
发明人： NISHI KAZUHIKO , ISHII TAKATOSHI , YAMASHITA RIYOUZOU , OKUMURA TAKATOSHI , YAMAOKA NARIMITSU
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G5/00 , G09G5/02 , G09G5/12 , G09G5/393

29. 发明专利

JPS60245035A DISPLAY CONTROLLER 失效
公开(公告)号：JPS60245035A
公开(公告)日：1985-12-04
申请号：JP10030384
申请日：1984-05-18
申请人： ASCII CORP , NIPPON MUSICAL INSTRUMENTS MFG
发明人： NISHI KAZUHIKO , ISHII TAKATOSHI , YAMASHITA RIYOUZOU , OKUMURA TAKATOSHI , YAMAOKA NARIMITSU
IPC分类号： G06F3/153 , G06T11/00 , G09G5/02
摘要： PURPOSE:To use one color code as a transparent color code and also as a specific color code by providing plural registers and a transparent color code detecting circuit. CONSTITUTION:A register 9 is a one-bit register and 1 or 0 is written by a CPU2. A register 15, on the other hand, is a four-bit register and a color code is written by the CPU2. When the register 9 holds 1, the border area 4b on a display screen is displayed in a color (background color) corresponding to the color code in the register 15. Further, an image based upon color codes in a VRAM5, i.e. color codes of specific colors is displayed at the inside of the area 4b. Then, when the register 9 holds 0, zero detecting circuits 12, 13 both enter an enable state and the color codes are processed as transparent codes. Namely, one color code is usable as both the transparent color code and color code of a specific color.

30. 发明专利

JPS60225961A INTERRUPTION CONTROLLER OF CPU 失效
公开(公告)号：JPS60225961A
公开(公告)日：1985-11-11
申请号：JP8327384
申请日：1984-04-25
申请人： ASCII CORP
发明人： ISHII TAKATOSHI , YAMASHITA RIYOUZOU
IPC分类号： G06F13/38 , G06F9/48 , G06F13/24 , G06F15/78
摘要： PURPOSE:To further expand the function of a multiple-function CPU, by providing an interruption request port which checks the level condition of signals or internal condition of the multiple-function CPU and a register equipped with bits which inhibit or permit interruptions. CONSTITUTION:Address signals of address lines ADR0-ADR7 outputted from a CPU201 are decoded by an I/O address decoder 202 and select signals of each register/port 207-210 are outputted. The interruption controlling register 209 controls the enable/disable of expanding interruption requesting signals and the CPU201 checks that which expanding interruption requesting signal is generated by means of the interruption status port 210. Each interruption becomes enable only when each bit becomes ''1'' at the interruption status port 210 and each interruption is inhibited only when each bit becomes ''1'' at the interruption controlling register 209.

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