专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明专利

JP2010080523A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010080523A
公开(公告)日：2010-04-08
申请号：JP2008244576
申请日：2008-09-24
申请人： Toshiba Corp , 株式会社東芝
发明人： KUMURA YOSHINORI , KANETANI HIROYUKI
IPC分类号： H01L21/8246 , H01L27/10 , H01L27/105
CPC分类号： H01L28/57 , H01L27/11507 , H01L27/11509
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which suppresses deterioration in polarization characteristics of a ferroelectric capacitor by suppressing stress to the ferroelectric capacitor.
SOLUTION: The semiconductor memory device includes: a semiconductor substrate 10; the ferroelectric capacitor FC provided above the semiconductor substrate and including an upper electrode UE, a ferroelectric film FE and a lower electrode LE; and upper interlayer insulating films ILD3 and ILD4 provided enclosing a periphery of the ferroelectric capacitor, wherein a gap 50 is provided between the ferroelectric capacitor and upper interlayer insulating film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体存储器件，其通过抑制对铁电电容器的应力来抑制铁电电容器的极化特性的劣化。半导体存储器件包括：半导体衬底10; 设置在半导体基板上方并包括上电极UE，铁电体膜FE和下电极LE的铁电电容器FC; 并且上部层间绝缘膜ILD3和ILD4包围铁电电容器的周围，其中间隙50设置在铁电电容器和上层间绝缘膜之间。版权所有（C）2010，JPO＆INPIT

12. 发明专利

JP2008218842A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008218842A
公开(公告)日：2008-09-18
申请号：JP2007056403
申请日：2007-03-06
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI
IPC分类号： H01L21/8246 , H01L27/105
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To improve the shape and characteristics of a ferroelectric capacitor at the terminal end of a memory block in a semiconductor memory device.
SOLUTION: A semiconductor memory device includes: a switching Tr 14; a selection Tr 19 of which a diffusion layer 15 is electrically connected to a diffusion layer 15 of the Tr 14; a memory capacitor M00 being formed above the Tr 14 and including a lower electrode connected to the diffusion layer 15 of the Tr 14, a ferroelectric film formed on the lower electrode and an upper electrode formed on the ferroelectric film and connected to the diffusion layer 15 of the Tr 14; dummy capacitors DC00 and DC01 having the same structure as M00 and being formed above the selection Tr 19; a W-plug 16 connecting the diffusion layer 15 of the selection Tr 19 and a bit line BL formed above the M00, DC00 and DC01; and an Al-plug 17 connecting the lower electrodes of the DC00 and DC01 and the BL.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了改善半导体存储器件中存储块的终端处的铁电电容器的形状和特性。解决方案：半导体存储器件包括：开关Tr 14; 选择Tr 19，其中扩散层15电连接到Tr 14的扩散层15; 存储电容器M00形成在Tr 14上方，并且包括连接到Tr 14的扩散层15的下电极，形成在下电极上的铁电体膜和形成在强电介质膜上并连接到扩散层15的上电极的Tr 14; 具有与M00相同结构并形成在选择Tr 19上方的虚拟电容器DC00和DC01; 连接选择Tr 19的扩散层15和形成在M00，DC00和DC01上方的位线BL的W形插头16; 以及连接DC00和DC01的下电极和BL的Al插头17。版权所有（C）2008，JPO＆INPIT

13. 发明专利

JP2008135543A Nonvoltatile memory device and manufacturing method thereof 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：JP2008135543A
公开(公告)日：2008-06-12
申请号：JP2006320197
申请日：2006-11-28
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI
IPC分类号： H01L21/8246 , H01L27/105
CPC分类号： H01L28/57 , H01L28/56 , H01L28/65 , H01L28/75
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device with a dielectric capacitor having sufficient hydrogen barrier capability, and a manufacturing method thereof.
SOLUTION: The nonvolatile memory device includes a semiconductor substrate 20; a lower electrode 30 formed on the upper part of the semiconductor substrate 20; a ferroelectric capacitor 13 having a first ferroelectric film 31a formed on the lower electrode 30 and having unevenness on its upper surface, a second ferroelectric film 31b formed on the first ferroelectric film 31a and having an upper surface flatter than the first ferrodielectric film 31a, and an upper electrode 32 formed on the second ferroelectric film 31b; an insulative protective film 36 and a conductive protective film 38 formed on the upper electrode 32 and having hydrogen barrier capability; and a cell transistor 14 having a drain diffusion layer 26 connected to a bit line 11, a source diffusion layer 27 connected to the first electrode 30 and a gate 29 connected to a word line 12.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供具有足够的氢阻挡能力的介电电容器的非易失性存储器件及其制造方法。解决方案：非易失性存储器件包括半导体衬底20; 形成在半导体衬底20的上部的下电极30; 具有形成在下电极30上的第一铁电体膜31a并且在其上表面具有凹凸的铁电电容器13，形成在第一铁电体膜31a上并且具有比第一铁电体膜31a平坦的上表面的第二铁电体膜31b，以及形成在第二铁电体膜31b上的上电极32; 形成在上电极32上并具有氢阻挡能力的绝缘保护膜36和导电保护膜38; 以及具有连接到位线11的漏极扩散层26的单元晶体管14，连接到第一电极30的源极扩散层27和连接到字线12的栅极29。版权所有（C）2008， JPO＆INPIT

14. 发明专利

JP2008071899A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008071899A
公开(公告)日：2008-03-27
申请号：JP2006248511
申请日：2006-09-13
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI , KUNISHIMA IWAO
IPC分类号： H01L21/8246 , H01L27/105
CPC分类号： H01L27/11507 , H01L27/11502 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, a chain type FeRAM having a 1PEP_FeRAM capacitor structure, having a microscopic capacitor structure with its manufacturing yield improved.
SOLUTION: The semiconducrtor device comprises a semiconductor substrate 10; a transistor MT arranged on the semiconductor substrate and having a source-drain diffusion layers 26, 28, a gate insulating film 32 arranged on the semiconductor substrate between the source-drarin diffusion layers, and a gate electrode 30 arranged on the gate insulating film; an interlayer insulating film 8 arranged on the transistor MT, a plug electrode 12 arranged on one source-drain diffusion layer 26, and a plurality of ferroelectric capacitors C
FE arranged on the interlayer insulating layer and comprising a laminated structure of a lower electrode 14, a ferroelectric film 16, and an upper electrode 18. A pair of two ferroelectric capacitors have a common lower electrode 14 and a discrete upper electrode 18, the plug electrode is arranged under the pair of ferroelectric capacitors, and the whole surface of the plug electrode is covered by the lower electrode.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有1PEP_FeRAM电容器结构的链式FeRAM的半导体器件，具有微观电容器结构，其制造成品率得到改善。半导体器件包括半导体衬底10; 配置在半导体衬底上并具有源极 - 漏极扩散层26,28的栅极绝缘膜32和布置在源极 - 液体扩散层之间的半导体衬底上的栅极绝缘膜32和布置在栅极绝缘膜上的栅电极30; 布置在晶体管MT上的层间绝缘膜8，布置在一个源极 - 漏极扩散层26上的插塞电极12和布置在层间绝缘层上的多个铁电电容器C FE ，并且包括层压下电极14的结构，铁电体膜16和上电极18.一对两个铁电电容器具有共同的下电极14和分立的上电极18，插头电极设置在一对铁电电容器下方，并且插头电极的整个表面被下电极覆盖。版权所有（C）2008，JPO＆INPIT

15. 发明专利

JP2005327847A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005327847A
公开(公告)日：2005-11-24
申请号：JP2004143428
申请日：2004-05-13
申请人： Infineon Technologies Ag , Toshiba Corp , インフィネオンテクノロジースアクチエンゲゼルシャフト , 株式会社東芝
发明人： NATORI KATSUAKI , KANETANI HIROYUKI , YAMAKAWA KOJI , HORNIK KARL , HILLIGER ANDREAS
IPC分类号： H01L27/105 , H01L21/20 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, wherein damages in subsequent processes can be reduced.
SOLUTION: The semiconductor device has a capacitor constituted of a lower electrode (200), dielectrics (300), and an upper electrode (400). Further, the device is provided with first protective films (122, 123) which are in contact with the upper electrode and deposited by a sputtering method and have a columnar structure, and second protective films (124, 126) which are deposited by a CVD method on upper sides of the first protective films.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种半导体器件及其制造方法，其中可以减少后续处理中的损坏。解决方案：半导体器件具有由下电极（200），电介质（300）和上电极（400）构成的电容器。此外，该器件设置有与上电极接触并通过溅射法沉积并具有柱状结构的第一保护膜（122,123）和通过CVD沉积的第二保护膜（124,126）方法在第一保护膜的上侧。版权所有（C）2006，JPO＆NCIPI

16. 发明专利

JP2005310918A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005310918A
公开(公告)日：2005-11-04
申请号：JP2004123371
申请日：2004-04-19
申请人： Toshiba Corp , 株式会社東芝
发明人： NATORI KATSUAKI , KANETANI HIROYUKI , YAMAZAKI SOICHI , YAMAKAWA KOJI
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L23/522 , H01L27/115 , H01L31/113
CPC分类号： H01L27/11502 , H01L23/5223 , H01L27/11507 , H01L28/57 , H01L28/65 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, wherein a process is simplified, and an auxiliary capacitor having superior electrical characteristics is disposed in the peripheral circuit of a ferroelectric capacitor. SOLUTION: The semiconductor device comprises a semiconductor substrate (S), a ferroelectric capacitor (A), obtained by sandwiching a ferroelectric film (300) provided above the semiconductor substrate between a lower electrode (200) and an upper electrode (400); a protective film (124) formed to cover the ferroelectric capacitor; and an auxiliary capacitor (B) provided in a peripheral circuit part of the ferroelectric capacitor and formed by using the protective film as a capacitor insulating film. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种简化工艺的半导体器件，并且在铁电电容器的外围电路中设置具有优异电特性的辅助电容器。解决方案：半导体器件包括通过将设置在半导体衬底之上的强电介质膜（300）夹在下电极（200）和上电极（400）之间而获得的半导体衬底（S），铁电电容器（A））; 形成为覆盖所述铁电电容器的保护膜（124）以及设置在铁电电容器的外围电路部分中并通过使用保护膜作为电容器绝缘膜形成的辅助电容器（B）。版权所有（C）2006，JPO＆NCIPI

17. 发明专利

JP2005093605A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005093605A
公开(公告)日：2005-04-07
申请号：JP2003323330
申请日：2003-09-16
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAZAKI SOICHI , KANETANI HIROYUKI , TOMIOKA KAZUHIRO , YAMAKAWA KOJI
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L27/115 , H02H9/00
CPC分类号： H01L27/11507 , H01L27/11502 , H01L28/55 , H01L28/65 , H01L28/75
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a capacitor capable of preventing reduction in the thickness of a top electrode and also preventing the top electrode from being penetrated, and hence improved in quality, electric properties, and reliability.
SOLUTION: An etching stopper film 18 formed of a conductive material is so formed as to cover the top face of the top electrode 17 of the capacitor 13. Then, a hard mask film 19 formed of a material having an etch rate higher than that of the stopper film 18 is so formed as to cover the capacitor 13 and the stopper film 18. Upper layer wiring 21a for a bottom electrode formed on top of the hard mask film 19 is electrically connected to a bottom electrode 14 via a plug 22a for a bottom electrode. In parallel with this, upper layer wiring 21b for a top electrode formed on top of the hard mask film 19 is electrically connected to the top electrode 17 via a plug 22b for a top electrode and the stopper film 18.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种配备有能够防止顶部电极的厚度减小并且还防止顶部电极被穿透的电容器的半导体器件，因此提高了质量，电性能和可靠性。解决方案：由导电材料形成的蚀刻阻挡膜18形成为覆盖电容器13的顶部电极17的顶面。然后，由具有蚀刻速率更高的材料形成的硬掩模膜19 与阻挡膜18相比形成为覆盖电容器13和阻挡膜18.形成在硬掩模膜19的顶部的底部电极的上层布线21a经由插塞电连接到底部电极14 22a用于底部电极。与此并行地，形成在硬掩模膜19的顶部上的顶部电极的上层布线21b经由用于顶部电极的塞子22b和阻挡膜18电连接到顶部电极17.版权：（ C）2005，JPO＆NCIPI

18. 发明专利

JP2004349474A Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：JP2004349474A
公开(公告)日：2004-12-09
申请号：JP2003144869
申请日：2003-05-22
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI , KUNISHIMA IWAO
IPC分类号： H01L21/768 , G11C8/02 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11507 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To reduce damage due to a multi-layer manufacturing process for a dielectric capacitor employed in an FeRAM and prevent the film peeling of an interlayer insulating film.
SOLUTION: A protective film 7 is formed on the surface of the dielectric capacitor 6. A P-SiO
2 interlayer insulating film 8 having a dielectric constant not lower than 4 is formed on the protective film 7, and an Al wiring 10 for a first layer is formed on the P-SiO
2 interlayer insulating film 8. Further, a low-k interlayer insulating film 11 having a dielectric constant not higher than 4 is formed on the Al wiring 10, and an Al wiring 13 for a second layer is formed on the low-k interlayer insulating film 11. Low-k interlayer insulating films 14, 17 are formed in the same manner to constitute the FeRAM.
COPYRIGHT: (C)2005,JPO&NCIPI

19. 发明专利

JP2004022824A Semiconductor device and its manufacturing method 有权
公开(公告)号：JP2004022824A
公开(公告)日：2004-01-22
申请号：JP2002176029
申请日：2002-06-17
申请人： Infineon Technologies Ag , Toshiba Corp , インフィネオンテクノロジースアクチエンゲゼルシャフト , 株式会社東芝
发明人： KANETANI HIROYUKI , HILLIGER ANDREAS
IPC分类号： H01L27/105 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/10855 , H01L27/11507 , Y10S257/905
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, which can form a pair of capacitors in one photolithographic process and can reduce the occupied area of the pair of capacitors on a chip. SOLUTION: There are provided a semiconductor area 12 formed on the surface of a semiconductor substrate 11, a gate electrode 14 formed on the semiconductor substrate 11 between the semiconductor areas 12 via a gate insulating film 13, interlayer-insulating films 15, 16 formed on the semiconductor substrate 11, lower electrodes 18A, 18B formed on this interlayer insulating films, a contact plug 21A which is formed in the interlayer-insulating films 15, 16 and brought into contact with the lower electrode 18A, a contact plug 21B which is formed clear of the contact plug 21A in the interlayer-insulating films 15, 16 and brought into contact with the lower electrode 18B, ferroelectric films 19A, 19B formed on the lower electrodes 18A, 18B, respectively, and upper electrodes 20A, 20B formed on these ferroelectric films, respectively. COPYRIGHT: (C)2004,JPO

20. 发明专利

JP2011114330A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011114330A
公开(公告)日：2011-06-09
申请号：JP2009272519
申请日：2009-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI
IPC分类号： H01L27/105 , G11C11/22 , H01L21/8246 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having higher flexibility, in the selection of a bottom electrode material of a ferroelectric capacitor and having less via-processing, and to provide a method of manufacturing the semiconductor device.
SOLUTION: The semiconductor device includes switching transistors 301A and 301B formed on a substrate 101; a diffusion layer 121; an interlayer insulating film 131 formed on the transistor 301; ferroelectric capacitors 201A and 201B including a bottom electrode 211, a ferroelectric film 212 and a top electrode 213; a wiring layer 141, formed above the top electrode 213; a first plug TW that conducts electricity between the top electrode 213 and the wiring layer 141; second plugs V1A and V1B that conduct electricity between the diffusion layer 121 and the wiring layer 141; and a third plug CSF; disposed to the side of the bottom electrode 211 for making electrical continuity established between the bottom electrode 211 and the diffusion layer 121.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有较高柔性的半导体器件，在选择铁电电容器的底部电极材料并且具有较少的通孔加工，并且提供一种制造该半导体器件的方法。解决方案：半导体器件包括形成在衬底101上的开关晶体管301A和301B; 扩散层121; 形成在晶体管301上的层间绝缘膜131; 包括底部电极211，强电介质膜212和顶部电极213的铁电电容器201A和201B; 形成在顶部电极213上方的布线层141; 在顶部电极213和布线层141之间传导电力的第一插头TW; 第二插头V1A和V1B，其在扩散层121和布线层141之间导电; 和第三插头CSF; 设置在底部电极211的侧面，用于在底部电极211和扩散层121之间建立电连续性。版权所有：（C）2011，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式