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11. 发明专利

JPH01280318A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01280318A
公开(公告)日：1989-11-10
申请号：JP622389
申请日：1989-01-13
申请人： TOSHIBA CORP
发明人： FURUKAWA KAZUYOSHI , WATANABE KIMINORI , TANZAWA KATSUJIRO , FUKUDA KIYOSHI
IPC分类号： H01L21/762 , H01L21/306 , H01L21/316 , H01L21/76
摘要： PURPOSE:To remain an oxide film on a rear of a wafer without providing any special protection at the time of providing an opening to a mask oxide film by forming an oxide film which is thicker than an oxide film on a wafer surface to be provided with an opening on a rear of the wafer. CONSTITUTION:When manufacturing a semiconductor device through a process to eliminate a part of an oxide film 16 formed on a silicon wafer 11 to provide an opening, an oxide film 13' which is thicker than the oxide film 16 on the wafer 11 surface to be opened is formed in advance in the rear of the wafer. For example, water vapor oxidation is applied to the n-type silicon wafer 11 of a thickness of 500mum and surface azimuth (100), and an oxide film 13 of 1.1mum both sides, respectively is formed. The oxide wafers 111, 112 are bonded directly each other and one wafer 112 is polished to a remaining thickness of 50mum. Then the oxide film 16 for a mask is formed to a thickness of 0.5mum by water vapor oxidation. Resist 17 is applied to the bonded wafer and then patterned, which is thereafter used as a mask to provide an opening to the surface oxide film 16 by etching in ammonium fluoride solution.

12. 发明专利

JPS6457674A CONDUCTIVITY-MODULATION MOSFET 失效
公开(公告)号：JPS6457674A
公开(公告)日：1989-03-03
申请号：JP30463487
申请日：1987-12-03
申请人： TOSHIBA CORP
发明人： NAKAGAWA AKIO , WATANABE KIMINORI , YAMAGUCHI YOSHIHIRO
IPC分类号： H01L29/78 , H01L27/04 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/68 , H01L29/739 , H01L29/745
摘要： PURPOSE:To improve the switching characteristics in the case of turn-off without raising on-voltage by a method wherein a MOSFET effectively realizing an anode short structure, turning on only in the case of turn-on, is introduced to the drain side. CONSTITUTION:The first conductivity type base diffused layer 2 is selectively formed on a semiconductor wafer 1; the second conductivity type the first source diffused layer 3 is selectively formed on the surface of the base diffused layer 2; a source electrode 4 simultaneously in contact with the diffused layers 2, 3 is formed; and the first gate electrode 6 is formed on the surface region held by the source diffused layer 3 of the base diffused layer 2 and the wafer surface region through the intermediary of a gate insulating film 5. Furthermore, the first conductivity type drain diffused layer 8 different from the base diffused layer 2 is selectively formed; the second conductivity type the second source diffused layer 9 is selectively formed on the surface of the drain diffused layer 8; another drain electrode 10 simultaneously in contact with the diffused layers 8, 9 is formed; and the second gate electrode 12 is formed on the surface region held by the source diffused layer 9 of the drain diffused layer 8 and the wafer surface region through the intermediary of a gate insulating film 11.

13. 发明专利

JPS61222260A CONDUCTIVITY-MODULATION TYPE MOSFET 失效
公开(公告)号：JPS61222260A
公开(公告)日：1986-10-02
申请号：JP6442685
申请日：1985-03-28
申请人： TOSHIBA CORP
发明人： NAKAGAWA AKIO , YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI , OHASHI HIROMICHI
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10 , H01L29/41 , H01L29/417 , H01L29/739
摘要： PURPOSE:To suppress a latch-up phenomenon and to make it possible to operate at a large current, by providing a base layer, in which a source layer is not formed, among a plurality of base layers, providing an auxiliary electrode on said base layer, and passing carriers through a p-n junction and a Schottky barrier when the carriers penetrate a source electrode. CONSTITUTION:Among a plurality of base layers 13, source layers are formed in a specified number of the base layers, and the source layers are not formed in the other base layers. High-impurity p type layers 20 are formed in the base layers 13. In the base layer 131, in which the source layer 14 is formed, a source electrode 171, which is ohmic-contacted with both the source layer 14 and the base layer 131, is formed. In the base layer 132, in which the source layer is not provided, an anxiliary electrode 172 which is ohmic-contacted with the base layer 132, is formed. The electrode 172 is connected to the source electrode 171. A drain electrode 18 is formed on the back surface of a substrate 11 by evaporation of a V-Ni-Au film. In this constitution, of a hole currents, which are injected into the p-type base layer 13, the current passing a channel part 192 flows to the auxiliary electrode 172.

14. 发明专利

JPS61164263A CONDUCTIVE MODULATION TYPE MOSFET 失效
公开(公告)号：JPS61164263A
公开(公告)日：1986-07-24
申请号：JP487685
申请日：1985-01-17
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI , NAKAGAWA AKIO
IPC分类号： H01L29/78 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/739
摘要： PURPOSE:To prevent any latch up phenomenon up to high current regions from occuring by a method wherein the parts not forming source diffused layers are periodically provided in the first conductive type base layers while the width of source diffused layers coming into contact with source electrodes is made 10mum or less. CONSTITUTION:A part of source layers 14 is periodically removed to make the width of source diffused layers 14 coming into contact with source electrodes 17 10mum or less. The length l3 from a point (b) to parts 21 not forming the source diffused layers 14 is reduced less than half of the length of layers 14 so that the hole current at the point (b) in a channel part may flow easier into the parts 21 not forming the source diffused layers 14 than through the parts below the layers 14. Through these procedures, any latch up phenomenon up to high current regions may be prevented from occuring since the resistance in the lateral direction below the source diffused layers 14 may be effectively reduced less than that in any conventional structures.

15. 发明专利

JPS60196974A Conduction modulation type mosfet 失效
标题翻译：导体调制型MOSFET
公开(公告)号：JPS60196974A
公开(公告)日：1985-10-05
申请号：JP5281084
申请日：1984-03-19
申请人： Toshiba Corp
发明人： NAKAGAWA AKIO , WATANABE KIMINORI
IPC分类号： H01L29/78 , H01L29/10 , H01L29/739
CPC分类号： H01L29/1095
摘要： PURPOSE: To lower resistance, and to prevent the generation of a latch-up phenomenon up to a large current region by forming a first conductive type high impurity concentration layer in a region just under a source layer in a base layer.
CONSTITUTION: A gate oxide film 13 is formed on a p
+ type Si substrate 11, a gate electrode 14 is shaped on the oxide film 13, and boron is diffused in approximately 8μm while using the gate electrode 14 as a mask to form a p type base layer 15. Boron ions in the quantity of a dose of 1×10
15 cm
-3 are implanted, and n
+ type source layers 16 and a p
+ type layer 17 are shaped through sufficient heat treatment. The p
+ type layer 17 is shaped shallowly in the p type base layer 15, impurity concentration just under a junction is also larger than 7×10
17 cm
-3 , and the resistance of sections just under the source layers 16 can be lowered sufficiently up to sections in the vicinity of a channel region 20. The titled MOSFET, which does not operate as a thyristor up to approximately 1,000A/cm
2 and ON resistance thereof is sufficiently low, is obtained.
COPYRIGHT: (C)1985,JPO&Japio
摘要翻译：目的：为了降低电阻，并通过在基底层的原始层的正下方形成第一导电型高杂质浓度层，防止产生大电流区域的闭锁现象。构成：在ap +型Si衬底11上形成栅极氧化膜13，在氧化膜13上形成栅电极14，并且在使用栅电极14作为掩模的同时将硼扩散到约8μm，形成p 注入量为1×10 15 cm -3的硼离子，n +型源层16和ap +型层17通过充分的热处理成型。 p +型层17在p型基极层15中形成浅，杂质浓度也大于7×10 17 cm -3，源极层16正下方的电阻可以充分地降低到通道区域20附近的部分。获得不高达大约1,000A / cm 2的晶闸管的功率的标称MOSFET和其导通电阻足够低。

16. 发明专利

JP2014038889A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014038889A
公开(公告)日：2014-02-27
申请号：JP2012178948
申请日：2012-08-10
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIRAI KOJI , IKIMURA TAKEHITO , WATANABE KIMINORI
IPC分类号： H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/088 , H01L27/092 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having high resistance against surge current.SOLUTION: A semiconductor device according to an embodiment comprises: a first conductivity type first semiconductor layer; a second conductivity type second semiconductor layer provided on a part of the first semiconductor layer; a first conductivity type third semiconductor layer and a second conductivity type fourth semiconductor layer having an effective impurity concentration higher than an effective impurity concentration of the second semiconductor layer, which are provided on a part of the second semiconductor layer and alternately arranged along a first direction; a gate insulation film provided on the second semiconductor layer; and a gate electrode provided on the gate insulation film. A resistance value between a boundary face with the first semiconductor layer and a boundary face with the third semiconductor layer, which is a resistance value of the second semiconductor layer in a second direction orthogonal to the first direction is larger than a resistance value between a position corresponding to a midpoint of the third semiconductor layer and a position corresponding to a midpoint of the fourth semiconductor layer, which is a resistance value of the second semiconductor layer in the first direction.
摘要翻译：要解决的问题：提供具有高抗冲击电流的半导体器件。解决方案：根据实施例的半导体器件包括：第一导电类型的第一半导体层; 设置在第一半导体层的一部分上的第二导电类型的第二半导体层; 第一导电型第三半导体层和第二导电型第四半导体层，其具有比第二半导体层的有效杂质浓度高的有效杂质浓度，其设置在第二半导体层的一部分上，并沿着第一方向 ; 设置在所述第二半导体层上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。在与第一半导体层的边界面和与第三半导体层的边界面之间的电阻值是与第一方向正交的第二方向上的第二半导体层的电阻值的电阻值大于位置对应于第三半导体层的中点和与第四半导体层的中点对应的位置，该第四半导体层是第一半导体层的第一方向的电阻值。

17. 发明专利

JP2007142041A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007142041A
公开(公告)日：2007-06-07
申请号：JP2005331742
申请日：2005-11-16
申请人： Toshiba Corp , 株式会社東芝
发明人： ENDO KOICHI , SATO KUMIKO , WATANABE KIMINORI , YASUHARA NORIO , MATSUDAI TOMOKO , KAWAGUCHI YUSUKE
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/0847 , H01L29/456 , H01L29/4933
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving both lowering of gate resistance and turning the breakdown strength of an element high. SOLUTION: A gate electrode 6 is formed on a semiconductor substrate 1 via a gate insulating film 5. Dispersion regions 2 and 3 are formed on the surface of the semiconductor substrate 1 so as to sandwich the gate electrode 6. A high resistance layer 21 is so formed on the surface of the semiconductor substrate 1 so as to be connected electrically to the diffusion region 3. A low resistance layer 22 is so formed on the surface of the semiconductor substrate 1 as to be connected electrically to the high resistance layer 21. A drain electrode 23 is connected to the low resistance layer 22. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够实现栅极电阻降低并且使元件的击穿强度变高的半导体器件。解决方案：通过栅极绝缘膜5在半导体衬底1上形成栅电极6.在半导体衬底1的表面上形成分散区域2和3，以夹着栅电极6.高电阻层21形成在半导体衬底1的表面上，以便与扩散区3电连接。低电阻层22形成在半导体衬底1的表面上，以电连接到高电阻漏极电极23连接到低电阻层22.版权所有（C）2007，JPO＆INPIT

18. 发明专利

JPH02138774A CONDUCTIVITY MODULATION TYPE MOSFET 失效
公开(公告)号：JPH02138774A
公开(公告)日：1990-05-28
申请号：JP18739389
申请日：1989-07-21
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI , NAKAGAWA AKIO
IPC分类号： H01L29/68 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/739 , H01L29/78
摘要： PURPOSE:To improve a MOSFET in a switching characteristic at turn-off as keeping an ON-voltage low enough by a method wherein a second conductivity type diffusion layer is provided inside a drain layer, and a drain electrode is brought into contact with the diffusion layer. CONSTITUTION:An N -type base layer 1 is formed on a substrate 15, and an N -type diffusion layer 9 shallower than a drain layer 8 is selectively formed inside the drain layer 8 under a drain electrode 10. The N -diffusion layer 9 is directly contacted with the drain electrode 10. By this setup, a switching characteristic at turn-off can be improved as keeping the ON-voltage low enough.

19. 发明专利

JPH027473A CONDUCTIVITY MODULATION TYPE MOSFET 失效
公开(公告)号：JPH027473A
公开(公告)日：1990-01-11
申请号：JP15687488
申请日：1988-06-27
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO , WATANABE KIMINORI
IPC分类号： H01L29/68 , H01L29/08 , H01L29/739 , H01L29/78
摘要： PURPOSE:To speed up the turn-off operation without increasing an on-state voltage by arranging a plurality of openings on a drain layer and causing a drain electrode to come in contact with a base layer that is exposed to the surface. CONSTITUTION:A plurality of openings 12 are arranged on a drain layer 8 below a drain electrode 11. An n-type buffer layer 3 that is exposed to the surface of a semiconductor wafer is in direct contact with the drain electrode 11. On the openings 12, an n -type layer 13 of high impurity concentration is formed by diffusion between the drain electrode 11 and the n-type buffer layer 3 in order to provide a low-resistant ohmic contact. The turn-off operation is performed by applying either a negative bias or zero bias voltage to a gate electrode 6. The anode-short structure that has adopted liberates the stored electrons out rapidly, thereby allowing a high-speed turn-off operation.

20. 发明专利

JPS6381857A MANUFATURE OF INSULATED-GATE SELF TURN-OFF THYRISTOR 失效
公开(公告)号：JPS6381857A
公开(公告)日：1988-04-12
申请号：JP22673586
申请日：1986-09-25
申请人： TOSHIBA CORP
发明人： SHINOHE TAKASHI , NAKAGAWA AKIO , WATANABE KIMINORI , YAMAGUCHI YOSHIHIRO
IPC分类号： H01L29/744 , H01L29/74 , H01L29/745 , H01L29/749
摘要： PURPOSE:To remove influence of discrepancy of mask positioning at manufacture of an insulated gate self turn-off thristor by a method wherein the pattern of a first mask material is formed at the same time with a gate electrode, the edge part of a second emitter layer is defined by the mask material thereof, and the second emitter layer is formed by selfalignment at the center part in the well of the insulated gate element for turn-off. CONSTITUTION:On a substrate, on which an n-type base layer 2 and a p-type base layer 3 are formed on a p type emitter layer 1, a gate electrode 51 is formed by a polycrystalline silicon film interposing a gate insulating film 4 between them. At this time, an island type first mask material 52 is formed separated by the prescribed distance from the gate electrode 51 using a polycrystalline silicon film the same with the gate electrode 51. After then, a second mask material 6 to cover the gap between the gate electrode 51 and the first mask material 52 is formed according to a photo resist, for example. Moreover, a mask is formed at the center part of an n-type well 8, and p-type impurities are doped using the mask thereof and the gate electrode 51 as masks to form a p type source layer 9. Accordingly, the so-called DSA-type MOSFET to serve as the insulated gate element for turn-off can be formed.

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