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11. 发明专利

JPS5688532A DATA TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPS5688532A
公开(公告)日：1981-07-18
申请号：JP16663279
申请日：1979-12-21
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU , MOTOMURA NOBUFUMI , MUNAKATA AKIO
IPC分类号： G06F13/12 , G06F3/00 , G06F13/00 , H04L29/10
摘要： PURPOSE:To make it possible to receive continuously data of variable length by writing reception state information at the head of data under a group of commands chained in both normal and opposite directions, by a communication controller of HDLC procedure. CONSTITUTION:On the basis of initial command Read 0, the communication controller places the 1st data buffer area 6, indicated by command, in an empty state and then advances. When the next command Read 1 is received, #1 frame data are transferred from data buffer area 7 and when the address is filled up, the program is skipped to store them in buffer area 8 under command Read 2. After the reception of #1 frame data is completed in this way, an advance to initial command Read 0 is reversely made under the commands chained in the opposite direction to store reception stat information in the 1st data area 6 and a return to the end position is made under the commands chained in the normal direction to start the reception of the next frame data. Consequently, the reception state information can be supplied to a host data processor together with the frame data.

12. 发明专利

JPS5469346A SHIFT CIRCUIT 失效
公开(公告)号：JPS5469346A
公开(公告)日：1979-06-04
申请号：JP13716577
申请日：1977-11-14
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU
IPC分类号： G06F7/00 , G01M11/00 , G06F5/01 , G06F7/76
摘要： PURPOSE:To simplify a circuit and increase the speed of operation in the circuit which executes shift control of palarell data of a digital computer by reducing the number of stages of shift elements and unifying shift control of both positive and negative directions to remove redandancy of the circuit. CONSTITUTION:The number of shifts outputted from shift number command part SN is applied to shift control part SFTCONT and is decoded, so that ternary signals are sent to respective shift elements + or -1 to + or -9. When the applied shift number is a binary number, it is applied after converting it a ternary number. Then signals of 0 and + or -1 is sent from shift control part SFTCONT to each gate of shift elements + or -1 to + or -9 and the gate of corresponding bit is opened to execute shift operation. By the constitution, the number of stages of shift elements is decreased, so that the circuit is simplified and operation at a high speed is available.

13. 发明专利

JPS60156154A CONSOLE SWITCHING SYSTEM 失效
公开(公告)号：JPS60156154A
公开(公告)日：1985-08-16
申请号：JP1126484
申请日：1984-01-25
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU , HANAZAWA AKIO , CHIBA HIDEAKI
IPC分类号： H04L29/14 , G06F11/20 , G06F13/00
摘要： PURPOSE:To obtain information necessary for maintenance and operation and to operate by a command input by enabling a console to work under control of a processor for communication control when an auxiliary processor is at fault. CONSTITUTION:Normally, the console 7' is connected to the auxiliary processor 5' through a change-over switch 10, and input/output for maintenance and operation are processed by the auxiliary processor 5'. When, for some reason, the auxiliary processor 5' goes to wrong state, and the console 7' is made unable to use, a maintainer operates the change-over switch 10 to switch it to a circuit connection 2' side. Then, the console is made usable under control of a processor 4'. That is, one of containable circuits of the circuit connection section 2' is registered beforehand for the console 7' to make control of the console separately from other ordinary circuits.

14. 发明专利

JPS60142458A ADDRESS DECISION SYSTEM 失效
公开(公告)号：JPS60142458A
公开(公告)日：1985-07-27
申请号：JP25002783
申请日：1983-12-28
申请人： FUJITSU LTD
发明人： HANAZAWA AKIO , HIGUCHI TAIHOU , CHIBA HIDEAKI
IPC分类号： G06F13/14 , G06F13/12
摘要： PURPOSE:To provide the address decision system of an I/O control device which is reduced at its address setting restriction by forming an address defining storage part for storing whether the addresses of the whole sub-channels are defined or not. CONSTITUTION:A service processor 10 reads out a sub-channel NSC address related to an interface A/B and information related to an ESC address, forms the corresponding information and transfers the formed information in channel adaptors 111-11n. In each of the channel adaptors 111-11n, an SVP link control circuit 15 receives said information and sets up the information in a local storage address register 18, a local storage data register 17 and a local storage control register 16 on the basis of scan-in operation. When a write access indication is supplied to the register 16, the address definition information is written in the corresponding position. An address decision circuit 21 reads out the contents of the corresponding in a local storage 20 and decides the contents.

15. 发明专利

JPS59119941A CIRCUIT CONNECTION SYSTEM 失效
公开(公告)号：JPS59119941A
公开(公告)日：1984-07-11
申请号：JP22842482
申请日：1982-12-27
申请人： FUJITSU LTD
发明人： HANAZAWA AKIO , HIGUCHI TAIHOU , HIWATARI AKITO
IPC分类号： H04L12/43
摘要： PURPOSE:To attain the direct connection to a loop transmission line without a changing a communication controller by providing a buffer memory means containing a region equivalent to plural channels for storage of parallel data, and memory means for both serial-parallel and parallel-serial conversions. CONSTITUTION:The serial data supplied from a loop transmission line is converted into a parallel form by a serial-parallel conversion register S/P, and the synchronism is obtained by a frame control circuit through a frame header part included in the serial data. Thus the time slot numbers are recognized within a frame. The frame data is temporarily set at a data buffer BM. At the same time, a local storage LS1 for serial-parallel conversion used for transmission is set between the buffer BM and a common control circuit together with a local storage LS2. Thus an interface same as a conventional one is used for transfer of data with a communication controller.

16. 发明专利

JPS5817749A MULTI-ADDRESS CALLING SYSTEM 失效
公开(公告)号：JPS5817749A
公开(公告)日：1983-02-02
申请号：JP11593781
申请日：1981-07-24
申请人： FUJITSU LTD
发明人： MORIKAWA HISASHI , HIGUCHI TAIHOU
IPC分类号： H04L12/18
摘要： PURPOSE:To perform multi-address calling with one packet, without changing a packet format, by providing a multi-address calling channel and a multi-address calling channel detector for a communication device. CONSTITUTION:A terminal a11 designates a loop number of itself to a loop number designation area, a communication device name A of the station to a communication device designation area 14, a channel number a1n for multi- address calling of own station to a channel number designation area 15, and transmits a packet written in data to a data area 16. This packet circulates a loop and returns to a device A of the designated area 14. The device A recognizes the end of the multi-address calling of the packet itself with a detection circuit and other communication devices B1-Bn detect the loop, communication device name and channel number and recognize the multi-address calling from the number a11 of the device A.

17. 发明专利

JPS57141134A COUNTER CIRCUIT 失效
公开(公告)号：JPS57141134A
公开(公告)日：1982-09-01
申请号：JP2721681
申请日：1981-02-26
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU , HIWATARI AKITO
IPC分类号： H03K21/40 , H03K21/34
摘要： PURPOSE:To achieve[1+]or[+2]counting by adding a carry output circuit and a counting inhibition controlling circuit. CONSTITUTION:A binary-coded 2N-scale counter which has a parity predicting circuit 1 and performs[+1]counting is provided additionally with a circuit 14 which inhibits a carry input from a lower-order digit to a count input of the most significant digit bit 2N by an external count number controlling signal CNT2, and a circuit 2' which selectively outputs a carry output to the outside by the count number control signal as AND between the states of respective bits including the most significant digit bits and the carry input or AND between the states of respective bits other than the most significant digit bit and the external carry input. According to the state of the number controlling signal CNT2,[+1]or[+2]counting is performed. Thus, minimum circuit elements are added to enable both[+1]counting and[+2]counting.

18. 发明专利

JPS5523668A TERMINAL CONNECTION SYSTEM 失效
公开(公告)号：JPS5523668A
公开(公告)日：1980-02-20
申请号：JP9696378
申请日：1978-08-09
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU , HOSONO FUMIO , HIWATARI AKITO
IPC分类号： H04L29/10 , G06F13/00 , H04L13/00
摘要： PURPOSE:To reduce the cost by making unnecessary the MODEM between the terminal and the adaptor, by providing the signal generation means of carrier detection and transmission enable at the line adaptor between the communication control unit and the terminal, and folding means to the signal from the terminal. CONSTITUTION:The direct connection line adaptor 4 is provided between the communication control unit main body 6 and the terminal 2. The unit ready signal ER from the terminal 2 is folded as the data set ready signal DR, and the transmission request signal RS from the terminal 2 is folded as the transmission enable signal CS. The signals ER and RS from the terminal 2 are inputted to the gate 6 and outputted as the carrier detection signal CD. The unit ready signal ER and the transmission request signal RS in the adaptor 4 are inputted to the gate 7 to form the carrier detection signal CD to the terminal and the transmission enable signal in the adaptor CS. Thus, the part between the terminal 2 and the adaptor 4 is the same interface as via the MODEM, and the terminal can perform the same operation as the connection of MODEM.

19. 发明专利

JPS60254856A CIRCUIT TROUBLE DETECTING CIRCUIT 失效
公开(公告)号：JPS60254856A
公开(公告)日：1985-12-16
申请号：JP11123484
申请日：1984-05-31
申请人： FUJITSU LTD
发明人： HIGUCHI TAIHOU , NAKAMURA TAKASHI , CHIBA HIDEAKI
IPC分类号： H04L29/14 , H04L13/00
摘要： PURPOSE:To reduce the cost of the level detection of a circuit interface by converting a selected signal to be measured into a multi-bit digital signal and analyzing it by a subprocessor on the basis of a signal which is inputted and outputted through a normal route. CONSTITUTION:A communication controller when predicting that trouble occurs in a circuit system sends an indication signal for selecting a signal of a circuit to the subprocessor. A selective specifying register 318 holds this signal and sends it out to an electronic switch 316 to select one signal. The selected signal is converted by an analog/digital converting circuit 317 into a logical signal consisting of plural bits, which is sent out to the subprocessor through a connection line 320. The subprocessor compares this signal with a signal which is received by a circuit scanner 32 through a register and arithmetic circuit 315 to decide and indicate whether or not trouble occurs at a side closer to a communication device than register converters 311-314.

20. 发明专利

JPS60243746A ADDRESS CONTROL SYSTEM 失效
公开(公告)号：JPS60243746A
公开(公告)日：1985-12-03
申请号：JP9993284
申请日：1984-05-18
申请人： FUJITSU LTD
发明人： NAKAMURA TAKASHI , HIGUCHI TAIHOU , CHIBA HIDEAKI
IPC分类号： G06F9/46 , G06F9/30 , G06F9/48 , G06F12/02
摘要： PURPOSE:To use an address area effectively without using a limited address area exclusively at the time of a specific travelling level by changing the definition of a part of memory and register groups in accordance with the travelling level of a program. CONSTITUTION:The program can access a register RL1 and a memory area M11 corresponding to address selecting signals r0-rm and MAx-MAy prepared for initializing and diagnosis operation setting only when the travelling level is L1, but can not access by other travelling levels L2-Ln. In the travelling levels other than L1, all the address areas A0-An can be used independently of the register RL1 and the memory area M11 and all the areas of memories 16, 17, etc. of addresses other than the register RL1 and the memory area M11 corresponding to address selecting signals R0-Ri can be optionally accessed.

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