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11. 发明专利

JPH02148953A CHARGE CONDITION TRANSFER EXCHANGE METHOD 失效
公开(公告)号：JPH02148953A
公开(公告)日：1990-06-07
申请号：JP30047588
申请日：1988-11-30
申请人： HITACHI LTD
发明人： YAMAGUCHI KANMI , YAMAMOTO YUSUKE , OKAJIMA KEISUKE , KUSABA KEIZO
IPC分类号： H04M3/42 , H04M15/16
摘要： PURPOSE:To recognize the charge condition of a communication network at a terminal equipment by providing a means transferring the charge condition of a communication charge at every communication prior to the start of communication from the communication network to the terminal equipment after the communication request from the terminal equipment to the communication network. CONSTITUTION:An outgoing terminal equipment A dials the telephone number of an incoming terminal equipment and its service number. An exchange B receives dial information from an outgoing terminal equipment B and indexes sequentially a charge condition calculation table 13 by using an incoming station number 141, a service number 142 and a communication time band type 143 included in a called terminal equipment telephone number 14 to obtain a charge condition MBI 15. Moreover, the exchange B uses the obtained charge condition MBI 15 to apply charge condition notice in voice to the outgoing terminal equipment A. Thus, the outgoing terminal equipment recognizes the call charge condition in voice.

12. 发明专利

JPS59225471A PROCESSOR INDEPENDENT RISE SYSTEM 失效
公开(公告)号：JPS59225471A
公开(公告)日：1984-12-18
申请号：JP9954083
申请日：1983-06-06
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE , MITAMURA TAKASHI
IPC分类号： G06F11/18 , G06F15/16 , G06F15/177 , G06F11/00
摘要： PURPOSE:To improve the service and to simplify the processing by rasing a rise request to a processor rise circuit to reduce the time of the rise of each processor and the entire system. CONSTITUTION:When a processor stop counter 5001 is counted up by a processor stop monitoring circuit 1002, the count value within a prescribed time is decoded. When the count value is a rise execution permissible number of times or below at each prescribed time, a processor rise request is given to a processor rise circuit 1001. Thus, the circuit 1001 conducts a prescribed operation to execute the rise of program without requiring the assistance of other processors. Should all processors 100-10n be in a fixed fault, a system rise discriminating circuit 600 is operated to raise the rise request to all the processors 100-10n via independent rise controllres 500-50n. Then the processor is started independently to rise the system.

13. 发明专利

JPS6086640A DUAL MEMORY COPY SYSTEM 失效
公开(公告)号：JPS6086640A
公开(公告)日：1985-05-16
申请号：JP19430583
申请日：1983-10-19
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE
IPC分类号： G06F11/16 , G06F12/16
摘要： PURPOSE:To improve the throughput by providing a device which performs the copying processing of a duplex memory and adding a memory copy indicating instruction to a processor. CONSTITUTION:When a processor 101 copies contents of a duplex memory 201 to a memory 202 to equalize contents of them to each other, the memory 202 is connected to an address bus 401 and an answer bus 301 to set the state where the same contents are written in both systems by a write operation. Next, the memory copy indicating instruction is executed, and a control instruction is executed, and then, control information consisting of an instruction part and a copy last address is stored in a buffer register 601 through the address bus 401. When the instruction part is decoded by an instruction decoder 602 to discriminate the copy indicating instruction, an answer is returned to the processor 101 through the answer bus 301 by an answer returning circuit 603. Only the time required for copying is counted in the processor side, and the copying processing is terminated with timing out. Thus, the throughput is improved.

14. 发明专利

JPS547252A PROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS547252A
公开(公告)日：1979-01-19
申请号：JP7207577
申请日：1977-06-20
申请人： HITACHI LTD
发明人： TOKITA YOSHIAKI , OKAJIMA KEISUKE
IPC分类号： G06F9/46 , G06F7/78 , G06F13/364 , G06F15/16 , G06F15/167 , G06F15/177
摘要： PURPOSE:To facilitate an easy information transfer between processors by installing a hard cue between processors and also adding an exclusive order for hard cue control to the processor.

15. 发明专利

JPH01292992A SUBSCRIBER INFORMATION MANAGING SYSTEM 失效
公开(公告)号：JPH01292992A
公开(公告)日：1989-11-27
申请号：JP12174588
申请日：1988-05-20
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE , KUSABA KEIZO
IPC分类号： H04Q3/545 , H04M3/00
摘要： PURPOSE:To eliminate the need of a new development of a subscriber information conversion/transfer exclusive program by constituting the title system so that all subscriber information is stored in an exchange from a data base by a new data constitution, in case a data constitution of subscriber information held by the exchange is changed by following up a transfer of an operation file of the exchange to a new file. CONSTITUTION:In case the necessity for changing the data constitution of subscriber information by a subscriber 40 has been generated by following up a transfer of an operation file to a new file in said exchange 40, a transfer request of all the subscriber information contained in the subscriber exchange 40 is executed to a data base 10 through a common line data link 22, a signal transfer point 20, and a common line data link 22 from the exchange 40. On the other hand, all the subscriber information from the data base 10 to its request is stored in the exchange 40 by a new data format. In this way, the development of a subscriber data conversion/transfer program for a new operation file from an old operation file becomes unnecessary.

16. 发明专利

JPS54104215A SUPERVISORY SWITCHING SYSTEM FOR SIGNAL SUPPLY 失效
公开(公告)号：JPS54104215A
公开(公告)日：1979-08-16
申请号：JP1056478
申请日：1978-02-03
申请人： HITACHI LTD
发明人： WANAMI MASAO , OKAJIMA KEISUKE , SUZUKI TAHEI , TOKITA YOSHIAKI
IPC分类号： H04M3/22 , H04M19/02 , H04Q11/04
摘要： PURPOSE:To supply a signal to a subscriber's side without intermittence by enabling a signal-supply supervisory switching unit to detect automatically signal intermittence, in case of the fault of an in-use signal supply, without depending upon the control of a CPU and by agreeing time slots by supplying a stand-by signal to a delay circuit at the same time. CONSTITUTION:The telephone switching system which supplies various signal tones from a time-division telephone switching unit to subscriber's telephone set 71 through time-division switch 41 is equipped with signal-supply supervisory switching unit 1 at the output side of switch 41. Signal tones from in-use signal supply 11 and stand-by signal supply 12 prepared previously are allotted to different time slots of the highway at the incoming side of switch 41, a supervision over a signal from in-use signal supply 11 is exercised by unit 1, and its in-use signal is supplied to subscriber's telephone set 17 through switch 41. Then, when the in-use signal is cut off, unit 1 switches it to a signal from stand-by signal supply 12 automatically, and the same slot of switch 41 supplies a stand-by signal to subscriber's telephone set 17.

17. 发明专利

JPH02186741A HIGH SPEED COMMUNICATION METHOD OF INTER-PROCESSOR 失效
公开(公告)号：JPH02186741A
公开(公告)日：1990-07-23
申请号：JP497889
申请日：1989-01-13
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE , KUSABA KEIZO
摘要： PURPOSE:To realize high speed communication and to improve transfer capacity by giving storage destination addresses in a reception processor to respective cells and automatically storing communication information to a memory in accordance with the addresses in the reception processor. CONSTITUTION:Information to be communicated is written into the memory 120 in the processor 110. Furthermore, the leading address of communication information is written into a memory read circuit 154 in a cell resolution device 150, the number of transfer words into a word counter 151, storage address absolute/relative display and the storage destination address into a storage destination address register 152, and a header into a header register 153 in the processor 110. The circuit 154 reads specified words from the designated leading address from the memory 120 and transfers it to a message register 130. When the cell completes, the register 130 is synchronized with a buffer register 140, the completed cell is transmitted to a vacant time slot, and the cell concerned is transmitted to a reception module 300.

18. 发明专利

JPH01105653A SYSTEM FOR CONNECTING CALL THROUGH COMMUNICATION NETWORK 失效
公开(公告)号：JPH01105653A
公开(公告)日：1989-04-24
申请号：JP26160587
申请日：1987-10-19
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE , KUSABA KEIZO
IPC分类号： H04Q1/18 , H04M3/38
摘要： PURPOSE:To widely decrease traffic between a data base and a telephone station by instructing the stop of call connection and the cancel of the stop from the data base side of a center to an electric communication network in correspondence to the change of a charge condition. CONSTITUTION:When the telephone number of a called customer and the number of a calling person are sent to an area telephone station 109, in the area telephone station 109, the connection of the call through an area communication network 100 is not allowed in case that a shop display is set. Then, talking connection is executed and it is informed the customer. On the other hand, for a call connection stopping display to be controlled by the area telephone station 109, the set and cancel of the display are executed by an instruction from a data base 101 to control the charge condition per customer. Thus, since the instruction is given to the communication network only when charge information go to an arrears condition and the said arrears condition is canceled, the traffic between the data base and the telephone station is widely decreased.

19. 发明专利

JPS6065370A RESOURCE CONTROLLER 失效
公开(公告)号：JPS6065370A
公开(公告)日：1985-04-15
申请号：JP17297083
申请日：1983-09-21
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE , UDAKI HIROSHI
IPC分类号： G06F9/52 , G06F15/16 , G06F15/177
摘要： PURPOSE:To simplify the program processing and to improve the program processing capacity by using a circuit which controls the idle/fill state of resources and giving a resource control instruction to each processor. CONSTITUTION:When a processor 3 is going to catch the resources on a common memory 1, a resource catch instruction drives an address register 15 according to the address value of a resource catch address register 22 and reads the contents of a resource control memory 16 which stores the idle/fill state of resources to store them into a register 17. A resource idle/fill state deciding circuit 18 decide the idle/fill state for the contents of the register 17. In an idle state the resource number shown by the contents of the register 22 is sent to the processor by a resource number informing circuit 23. At the same time, this resource number is sent to the register 15 and the resources of the memory 16 are rewritten to a fill state. In such a way, a resource catching process is.

20. 发明专利

JPS5833772A PROCESSOR SWITCHING SYSTEM 失效
公开(公告)号：JPS5833772A
公开(公告)日：1983-02-28
申请号：JP13150481
申请日：1981-08-24
申请人： HITACHI LTD
发明人： OKAJIMA KEISUKE , KUSABA AKIRA
IPC分类号： G06F15/16 , G06F11/20 , G06F15/177
摘要： PURPOSE:To improve the performance, by providing a control information transfer means between processors and executing a duplicated processor switching instruction added to a system management processor for an exclusive instruction for a duplicated processor switching. CONSTITUTION:A processor switching instruction is sequence-controlled via a universal bus 101. The processor switching instruction consists of an order section and a switching processor designation section. The order section is switched at a decoder 1002 and the processor designation section is interpreted at a decoder 1003. In switching processors from a duplicated processor 102 to a 103, first, the switched processors 102 and 103 are stopped. The content of a processor instruction executing control register group 1021 is transferred to a register group 1031 in the 103, allowing to take over a JOB under processing in the processor 102 to the processor 103.

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