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11. 发明专利

JPH0581216A PARALLEL PROCESSOR 失效
公开(公告)号：JPH0581216A
公开(公告)日：1993-04-02
申请号：JP24109291
申请日：1991-09-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NAKAKOSHI JUNJI , HAMANAKA NAOKI , CHIBA HIROYUKI , HIGUCHI TATSUO , SHUDO SHINICHI , OGATA YASUHIRO , TAKEUCHI SHIGEO , TOBA TATSU
IPC分类号： G06F15/17 , G06F15/173 , G06F15/80
摘要： PURPOSE:To provide a parallel processor capable of attaining a parallel processing managing function and an I/O function without reducing the number of processors for executing parallel processing and the loading method of the parallel processor. CONSTITUTION:Cross bar switches 101 having 2 +1 ports are arrayed and a group of 2 processors 103 is connected to the cross bar switches 101. Processors 104 to 106 for executing the parallel processing managing function and the I/O function are connected to the residual switches 101 out of respective switches 101 and respective processors are connected to the switches 101 through cross-over switches 102. Consequently parallel processing is executed by the 2 +1 processors and the parallel processing managing function and the I/O function are executed by other processors independently of the parallel processing. In the case of loading the parallel processor, each processor in a processor group connected to a cross bar switch in a certain dimension is successively loaded.

12. 发明专利

JPH04291660A INTER-PROCESSOR COMMUNICATION METHOD AND ITS PARALLEL PROCESSOR 失效
公开(公告)号：JPH04291660A
公开(公告)日：1992-10-15
申请号：JP5646991
申请日：1991-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HAMANAKA NAOKI , NAKAKOSHI JUNJI , HIGUCHI TATSUO , CHIBA HIROYUKI , SHUDO SHINICHI , TAKEUCHI SHIGEO , OGATA YASUHIRO , TOBA TATSU
IPC分类号： G06F9/46 , G06F12/08 , G06F12/10 , G06F15/16 , G06F15/17 , G06F15/177
摘要： PURPOSE:To reduce the overhead of data copying for buffering in an OS in the case of sending data to a network for inter-processor communication between parallel processors. CONSTITUTION:A PATH table 30 for finding out a cluster number and the page table origin of another processor from a virtual communication line (PATH) from one processor to the other processor is included in an OS area 29 in a memory corresponding to the processors. At the time of transmitting data, a cluster number and a page table origin are found out from the table 30 based upon the PATH specified by a transmission instruction and the value of the page table origin, a virtual address and data directly read out from the processor area are transmitted to the cluster specified by the cluster number. A receiving side cluster executes the address conversion of the virtual address and directly stores data in its processor area.

13. 发明专利

JPH04162161A STORAGE CONTROLLER 失效
公开(公告)号：JPH04162161A
公开(公告)日：1992-06-05
申请号：JP28705790
申请日：1990-10-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ARASAWA NOBUYUKI , NAKAKOSHI JUNJI , TAKEUCHI SHIGEO
IPC分类号： G06F12/16
摘要： PURPOSE:To eliminate the overhead caused by the interruption of an access given to a storage pert by holding a rewriting request of the corrected date in an error flip-flop and rewriting the data after detecting the time when no access request is received. CONSTITUTION:A rewriting address register 5 and a correction data register 6 are held as long as an error flip-flop 19 is kept set. An access detecting circuit 15 detects a fact through an inverter and an AND gate that the flip-flop 19 is set and no access request 4 is received. Then the circuit 15 performs the switch between the selectors 7 and 8 to output the contents of the register 5 to a memory address 11, to output the contents of the register 6 to the memory write data 9, to output a rewriting request 10 as a write enable signal 14 through an OR gate 22, and to write the corrected data in a memory 12. As a result, the overhead due to a rewriting operation can be eliminated.

14. 发明专利

JPH02132548A DEBUG BACK-UP SYSTEM FOR PARALLEL PROCESSOR 失效
公开(公告)号：JPH02132548A
公开(公告)日：1990-05-22
申请号：JP28565188
申请日：1988-11-14
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , TANAKA TERUO , HAMANAKA NAOKI , OMODA KOICHIRO , NAGASHIMA SHIGEO
IPC分类号： G06F11/28 , G06F15/16 , G06F15/177
摘要： PURPOSE:To improve the program debugging efficiency for the parallel processors by informing a programmer of a fact that the transfer data is superscribed. CONSTITUTION:In a processor of the data reception side, a valid bit V is read out of an associative memory 124 and sent to an associative memory superscription controller 201 via a signal line 150 when a data packet 102 is received from a data transfer line 101. The controller 201 fetches the transfer data (Data) and a data identifier (Key) which are read out of the memory 124 at one time and informs an instruction processor 140 of the occurrence of the superscription via a signal line 202 when the bit V shows 1. The processor 140 receives both the Data and the Key from the controller 201 via a signal line 203 and reports this result to a control processor. As a result, the program debugging efficiency is improved for the parallel processors.

15. 发明专利

JPH0218732B2 失效
公开(公告)号：JPH0218732B2
公开(公告)日：1990-04-26
申请号：JP3407383
申请日：1983-03-02
申请人： HITACHI LTD
发明人： JU KEIICHI , TSUNEHIRO TAKASHI , NAKAKOSHI JUNJI , NAKAI KOICHI
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38

16. 发明专利

JPH01113850A PARALLEL COMPUTER 失效
公开(公告)号：JPH01113850A
公开(公告)日：1989-05-02
申请号：JP27018387
申请日：1987-10-28
申请人： HITACHI LTD
发明人： HAMANAKA NAOKI , TANAKA TERUO , NAKAKOSHI JUNJI , OMODA KOICHIRO , NAGASHIMA SHIGEO , OSHIMA KAZUO
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80
摘要： PURPOSE:To reduce the load of a user by using a validity holding means which decides the validity or invalidity of the result of conversion and preventing the data transmitting action designated by a program when the specific value is held by said holding means. CONSTITUTION:A #1 processor element 3-1 is inhibited to transmit data even though it is designated by a program to transmit the data to the west or the north of the element 3-1 since a fact is set at a validity holding means 101 that the corresponding conversion is invalid. In case the element 3-1 tries to receive data from the west or the north, the data is supplied from a data holding means 104 corresponding to the means 101 not from a network via a data selection means 105 since said invalidity of conversion is set at the means 101. Thus the values 50 and 100 are turned into the reception data. The same action is carried out also with other processors. Thus it is just required to develop, maintain and control the only common program.

17. 发明专利

JPS6432379A COMPUTER 失效
公开(公告)号：JPS6432379A
公开(公告)日：1989-02-02
申请号：JP18752987
申请日：1987-07-29
申请人： HITACHI LTD
发明人： HAMANAKA NAOKI , TANAKA TERUO , OMODA KOICHIRO , NAGASHIMA SHIGEO , NAKAKOSHI JUNJI , OSHIMA KAZUO
IPC分类号： G06F17/16 , G06F15/78 , G06F15/80
摘要： PURPOSE:To quickly transmit and receive vector data by executing the vector data storing operation and the vector data loading operation in parallel. CONSTITUTION:At the time of transferring vector data from a vector processor 100 to a parallel processor 200 through a main storage 3, a synchronous store circuit 107 is started by a vector instruction control part 101. Then, data is successively read out from vector registers 103 and is sent to the store circuit 107. As the result, '1' is set to values of a first element, a second element, - of a vector semaphore register 1 while storing element data of the second register 103 to addresses 100, 104- of the main storage 3 in order from the first data. Meanwhile, an element processor 202-j loads data from the main storage 3 to the register having address 0 after the j-th element of vector data is written in the main storage and the j-th element of the register 1 is set to '1'. The similar operation is performed in case of the opposite case. Thus, both processors are simultaneously operated and vector data is quickly transmitted and received.

18. 发明专利

JPS61206082A PART DELETING CONTROL CIRCUIT 失效
公开(公告)号：JPS61206082A
公开(公告)日：1986-09-12
申请号：JP4654685
申请日：1985-03-11
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , AOSHIMA TOSHIHISA , TSUJIOKA SHIGEO
IPC分类号： G06F3/153 , G06F3/14 , G06T15/00
摘要： PURPOSE:To delete a desired pattern only by comparing the depth value stored at a Z buffer with that of the pattern to be deleted for each pixel and writing the value for the deleting condition only to the pixel value close to the observer. CONSTITUTION:A display processor 301 generates the depth value of the pattern, an address, an access request signal, etc., which are displayed for each pixel in respective pattern scopes, to a Z buffer and a controller 303. Luminance information of the pattern displayed, an address, etc., are generated at a frame buffer controller 303. An access control circuit 308, when an access request signal is received, sets the depth value of the pattern to a comparing register 310, reads the depth value from a Z buffer 305 in accordance with the address and sets to a register 311. A comparator 312 compares registers 310 and 311 and generates the result at the access control circuit 308. When as the comparing result, the depth value of the pattern is closer to the observer than the depth value read from the Z buffer, the contents of the register 310 are written in the Z buffer 305 and the writing of the luminance information is permitted.

19. 发明专利

JP2590154B2 失效
公开(公告)号：JP2590154B2
公开(公告)日：1997-03-12
申请号：JP31192787
申请日：1987-12-11
申请人： HITACHI LTD
发明人： NAKAKOSHI JUNJI , HAMANAKA NAOKI , TANAKA TERUO , OMODA KOICHIRO , NAGASHIMA SHIGEO , OSHIMA KAZUO
IPC分类号： G06F11/28 , G06F15/16 , G06F15/173

20. 发明专利

JPH07262155A PARALLEL COMPUTER AND MESSAGE BROADCASTING METHOD 失效
公开(公告)号：JPH07262155A
公开(公告)日：1995-10-13
申请号：JP5340594
申请日：1994-03-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HIGUCHI TATSUO , ISOBE TADAAKI , NAKAKOSHI JUNJI , TAKEUCHI SHIGEO , TOBA TATSU
IPC分类号： G06F15/173 , G06F15/16 , G06F15/163 , G06F15/80
摘要： PURPOSE:To enable plural processors to quickly broadcast messages without the occurrence of dead lock by providing a means, which indicates a broadcast request message, and a means which converts this message to a broadcast message by a repeating switch to which the broadcast message is not transmitted. CONSTITUTION:This method consists of processors (PE) 100, X-direction crossbar switches (XB-X) 132 to 135, Y-direction crossbar switches (XB-Y) 136 to 139, etc. At the time of data broadcasting to plural processors 100, the transmission processor newly provides a BR bit indicating the broadcast request message and sets this bit to '1' to transmit the broadcast request message to the network. A repeating switch (BEX) 120 transfers it to an extended XB-XO after setting the BR bit ands a BC bit to '0' and '1' respectively to convert it to a broadcast message. The XB-XO broadcasts it to EXOO to EXO3 and uses Y-direction XBs to broadcast it to all EXs, and the message is broadcasted from them to processors corresponding to EXs.

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