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11. 发明专利

JPS63152143A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63152143A
公开(公告)日：1988-06-24
申请号：JP29870986
申请日：1986-12-17
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118
摘要： PURPOSE:To improve the freedom in the design of a logical gate by providing power wirings adjacent to fundamental cells. CONSTITUTION:In a C-MOS array, numerous fundamental rows 3, which respectively consist of numerous fundamental cells 2, are provided in parallel to each other on the central part of a semiconductor chip 1. The regions among these cell rows 3 are each used as a wiring channel. Main line power wirings 4a and 4b are provided on the peripheries of these cell rows 3. The wiring 4a of these constitutes a wiring for feeding a power potential VDD to the cells 2 and input/output buffer cells 7 and the wiring 4b constitutes a wiring for feeding an earth potential VSS to the cells 2 and the cells 7. Moreover, power wirings 6a and 6b for feeding a power source to the cells 2 are provided in such a way as to pass through the center, for example, of a cell row 3. Hereby, as the connection of gate electrodes on the cells 2 to the power wirings and the connection of feeding contacts to the power wirings can be performbd, outside of the cells, the disposal of floating, pins and the feeding contact can be easily performed.

12. 发明专利

JPS6265343A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6265343A
公开(公告)日：1987-03-24
申请号：JP20420785
申请日：1985-09-18
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118
摘要： PURPOSE:To reduce the number of undistributed wirings and to improve a design operation efficiency by a method wherein the space between the unit cells of each unit cell row or the space between the unit cells of every prescribed number unit cells and the areas of the wiring areas are increased as the unit cell rows and the wiring areas are near the central part of a chip. CONSTITUTION:A device 1 is constituted in such a way that the number of the unit cells 4 of each unit cell block 4a and 4b is increased according as the blocks approach the central part of the device 1, whereby the wiring density at the central part can be reduced. Moreover, the device is constituted in such a way that the area of each wiring region 5a and 5b is increased according as the regions approach the central part of the device 1, whereby the number of the wirings which are connected to the logic circuit can be increased according as the wiring areas approach the central part, the wiring density at the central part can be reduced, in particular, the wiring density of the wirings which are formed extendedly in the line direction can be reduced. Furthermore, the device is constituted in such a way that the areas of wiring regions 5A-5C are increased according as the regions approach the central part of the device 1, whereby the number of the wirings which are connected to the logic circuit can be increased according as the wiring regions approach the central part, the wiring density at the central part can be reduced, in particular, the wiring density of the wirings which are formed extendedly in the column direction can be reduced.

13. 发明专利

JPS6140133B2 失效
公开(公告)号：JPS6140133B2
公开(公告)日：1986-09-08
申请号：JP10658877
申请日：1977-09-07
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/768 , H01L23/522 , H01L29/43

14. 发明专利

JPS61169021A LOGICAL INTEGRATED CIRCUIT 失效
公开(公告)号：JPS61169021A
公开(公告)日：1986-07-30
申请号：JP900785
申请日：1985-01-23
申请人： HITACHI LTD
发明人： KAWASHIMA MASATOSHI , TAKECHI MAKOTO
IPC分类号： H03K19/003 , H03K19/007 , H03K19/0175 , H03K19/173
摘要： PURPOSE:To prevent malfunction of an internal circuit by connecting a capacitor between an output node of an inverter of the 1st stage in an input buffer circuit and a power supply voltage terminal so as to reduce noise induced to an input pin. CONSTITUTION:A gate capacitance of, e.g., a P-channel MOSFETQ1 is connected between an output node n2 of the 1st stage inverter 1a and a power supply voltage Vcc. Thus, a gate electrode of the FET Q1 is connected to the output node n2 of the inverter 1a and the voltage Vcc is applied to a diffusion layer being a source and drain region of the FET Q1. Then the potential change in the node n2 slows dow by the gate capacitance of the FET Q1 connected to the inverter 1a and the potential at the node n2 is not lowered than a pre scribed voltage only when the potential at the node n1 exceeds a prescribed voltage for a slight period due to noise. As a result, no noise is introduced to the preceding internal circuit.

15. 发明专利

JPS6195545A Semiconductor ic device 失效
标题翻译：半导体IC器件
公开(公告)号：JPS6195545A
公开(公告)日：1986-05-14
申请号：JP21614784
申请日：1984-10-17
申请人： Hitachi Ltd
发明人： TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L27/118
CPC分类号： H01L27/11898 , H01L2224/05554
摘要： PURPOSE:To make it possible to connect electrically MISFETs of a first I/O cell and a second I/O cell for forming a buffer circuit, by providing a wiring region between a bonding pad and the I/O cells. CONSTITUTION:Gate insulating films 21A and 21B are formed, and gate electrodes 22A and 22B are formed. Next, an insulating film 28 is formed, and a connecting hole 29 is formed. Then, after a conductive layer 11 is formed, an insulating film 30 is formed. Then, a connecting hole is formed by removing the gate insulating films 21A and 21B and the insulating films 28 and 30 on semiconductor regions 23A and 23B. Subsequently, conductive layers 35, 36 and 37 are formed, an insulating layer 32 is formed, and the insulating films 30 and 32 on conductive layers 11J and 11I and a conductive layer 11E are removed, so as to form a connecting hole. Moreover, the conductive layer 36 and the insulating film 32 are removed, so as to form a different connecting hole. Next, after a conductive layer 27 and a bonding pad are formed, a protecting film is formed, and the protecting film on the bonding pad is removed to open a hole. By this method, a conductive layer for connecting electrically MISFETs of two I/O cells can be provided.
摘要翻译：目的：通过在接合焊盘和I / O单元之间提供布线区域，可以连接第一I / O单元的电气MISFET和用于形成缓冲电路的第二I / O单元。构成：形成栅绝缘膜21A和21B，形成栅电极22A和22B。接着，形成绝缘膜28，形成连接孔29。然后，在形成导电层11之后，形成绝缘膜30。然后，通过去除半导体区域23A和23B上的栅极绝缘膜21A和21B以及绝缘膜28和30来形成连接孔。随后，形成导电层35,36和37，形成绝缘层32，并且去除导电层11J和11I上的绝缘膜30和32以及导电层11E，以形成连接孔。此外，去除导电层36和绝缘膜32，以形成不同的连接孔。接下来，在形成导电层27和接合焊盘之后，形成保护膜，去除焊盘上的保护膜以打开孔。通过该方法，可以提供用于连接两个I / O单元的MISFET的导电层。

16. 发明专利

JPS59182540A Design for wiring pattern at semiconductor device 失效
标题翻译：设计用于半导体器件的布线图案
公开(公告)号：JPS59182540A
公开(公告)日：1984-10-17
申请号：JP5508383
申请日：1983-04-01
申请人： Hitachi Ltd
发明人： SATOU YASUO , TAKECHI MAKOTO
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/10 , H01L27/118
摘要： PURPOSE:To shorten delay time of wirings, and to precipitate the operating speed of a semiconductor device when wiring patterns to connect between cells are to be designed after the lines of the cells thereof are arranged regularly on a semiconductor chip by a method wherein a part of wiring channels on the chip is used as exclusive channels to be distinguished from other normal panels, and the wiring patterns intending to reduce delay logically is alloted preferentially onto the exclusive channels. CONSTITUTION:Cell lines 2 having terminals 3 along the longer direction are formed juxtaposing in three stairs, for example, positioning inside of bonding pads and input- output circuits no shown in the figure on a semiconductor chip 1. Then exclusive channels 40 in the inside lateral direction of the wiring channels are provided between the respective cell lines three pieces by three pieces and twelve pieces in total, and exclusive channels 41 in the lengthwise direction are formed three pieces by three pieces right, left and at the center, and nine pieces in total. Moreover, normal channels 50, 51 are arranged at the equal interval on the whole, the channels 50, 51 are used for wiring patterns 6 to connect between the normal terminals 3 whose wiring delays are out of consideration, and patterns 7-9 to connect between the terminals 3 intending to reduce wiring delays are wired using the channels 40, 41.
摘要翻译：目的：为了缩短布线的延迟时间，并且为了在半导体芯片上规则地布置其电池线之间的布线图案之间设计连接单元之间的布线图案时，缩短半导体器件的工作速度，的芯片上的布线通道被用作与其他普通面板区分开的专用通道，并且有意在逻辑上降低延迟的布线图案优先分配到专用通道上。构成：具有沿着较长方向的端子3的电池线2在三个楼梯中并列地形成，例如，在半导体芯片1上的图中未示出的接合焊盘和输入 - 输出电路内部定位。然后在内部的专用通道40 布线通道的横向方向总共设置在三个单元之间的三个单元和十二个单元格之间，并且沿长度方向的专用通道41由右，左和中心三个三部分形成，并且九个总共。此外，通常的通道50,51以相同的间隔整体布置，通道50,51用于布线图案6以连接正常端子3，其布线延迟不在考虑之中，而图形7-9连接旨在减少布线延迟的端子3之间使用通道40,41进行布线。

17. 发明专利

JPS5956760A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5956760A
公开(公告)日：1984-04-02
申请号：JP15328083
申请日：1983-08-24
申请人： Hitachi Ltd
发明人： TAKECHI MAKOTO , KAWAMOTO HIROSHI
IPC分类号： H01L27/10 , H01L21/8234 , H01L23/522 , H01L27/06 , H01L29/78
CPC分类号： H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE:To improve the integration degree by a method wherein a polycrystalline Si layer formed simultaneously with the gate of an Si gate MOS transistor Tr is decided as the first wiring layer, and then the film of an Si thermal oxide film is formed on the outer peripheral surface of the wiring layer by heat treatment in an oxidizing atmosphere. CONSTITUTION:Si oxide films 2 are formed on a P type Si substrate 1, and P Si layers 3 which prevent the generation of a parasitic MOS are formed under the films 2. A polycrystalline Si layer 7, the gate electrode, covered with an Si thermal oxide film 6 is arranged between a source layer 4 and a drain layer 5, and the Si gate MOS transistor MOS Tr8 is formed. The polycrystalline Si layers 9 and 10 serving as the first wiring layers are formed on the film 2. The Si thermal oxide film 12 is formed in the outer peripheral surfaces of the layers 9 and 10 except the part of connection to the second wiring layer. A polycrystalline Si layer 13 serving as the second wiring layer is formed on the upper surface thereof.
摘要翻译：目的：通过将与Si栅极MOS晶体管Tr的栅极同时形成的多晶Si层确定为第一布线层的方法来提高积分度，然后在外部形成Si热氧化膜的膜通过在氧化气氛中进行热处理而形成配线层的外周面。构成：在P型Si衬底1上形成Si氧化物膜2，在膜2之下形成防止寄生MOS的产生的P + 3层3.多晶Si层7，栅电极覆盖在源极层4和漏极层5之间配置Si热氧化膜6，形成Si栅极MOS晶体管MOS Tr8。用作第一布线层的多晶Si层9和10形成在膜2上。除了与第二布线层的连接部分之外，Si层氧化物膜12形成在层9和10的外周表面中。用作第二布线层的多晶Si层13形成在其上表面上。

18. 发明专利

JPS6349388B2 失效
公开(公告)号：JPS6349388B2
公开(公告)日：1988-10-04
申请号：JP15328083
申请日：1983-08-24
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO , KAWAMOTO HIROSHI
IPC分类号： H01L27/10 , H01L21/8234 , H01L23/522 , H01L27/06 , H01L29/78

19. 发明专利

JPS6329545A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6329545A
公开(公告)日：1988-02-08
申请号：JP17157586
申请日：1986-07-23
申请人： HITACHI LTD
发明人： SATO YASUO , TAKAHASHI TOSHIRO , TAKECHI MAKOTO
IPC分类号： H01L21/3205 , H01L21/82 , H01L21/822 , H01L21/8238 , H01L23/52 , H01L27/04 , H01L27/092 , H01L27/118
摘要： PURPOSE:To improve the degree of integration, by constituting reinforcing power source voltage interconnections, which are connected to main power source voltage interconnections at the peripheral part of a circuit block, which is formed by using basic cell lines. CONSTITUTION:Reinforcing power source voltage interconnections 15, which are connected to main power source voltage interconnections 5, are formed at the peripheral part of a circuit block MC, which is formed by a plurality of basic cell lines 7 arranged in the direction of rows. The power sources from the main power source voltage interconnections 5 are supplied together to the reinforcing power source voltage interconnections 15 through power-source feeding interconnections 16. The power sources are freely supplied into the circuit block MC or to the basic cell lines 7, 7A-7C other than the block from the reinforcing power source voltage interconnections 15. When the basic cell lines 7A-7C, which constitute circuits other than said circuit block MC, are present between the circuit block MC and the main power cource voltage interconnections 5, the reinforcing power source voltage interconnections 15 alleviate the restrictions on the arrangement of the circuits in the basic cell lines 7A-7C and the arrangement of the interconnection regions, and the using efficiency of the area is improved. Thus the degree of integration can be improved.

20. 发明专利

JPS6271248A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6271248A
公开(公告)日：1987-04-01
申请号：JP20996285
申请日：1985-09-25
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L27/118
摘要： PURPOSE:To prevent the integration of an entire gate array from decreasing by commonly using the gate of N- and P-type MOS transistors formed in a basic cell, and independently forming N- and P-type MOS transistors formed in a wiring channel adjacent thereto. CONSTITUTION:N- and P-channel MOS transistors Tn1-4, Tp1-4 of a basic cell 4 form a CMOS with the gates commonly used, N- and P-channel MOS transistors independent from the MOS transistors of the cell are formed in the wiring channels adjacent to the basic cell, connected with each other as required to form transmission gates TG1, TG2. Thus, a transmission gate can be readily formed without decreasing the integration of the basic cells.

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