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11. 发明专利

JPS5642486A TRUNK DEVICE 失效
公开(公告)号：JPS5642486A
公开(公告)日：1981-04-20
申请号：JP11734679
申请日：1979-09-14
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KUMASHIRO TADAHIKO , IMAGAWA HITOSHI , HASEGAWA KOUICHI , OBARA SUSUMU , SHIMOE TOSHIO
IPC分类号： H04M3/56 , H04M3/42 , H04M19/02 , H04Q3/42
摘要： PURPOSE:To realize incoming service during a call, conference calling service, etc., with the same constitution by selecting and supplying one of signals including a sound on the basis of a command from a processor to a conference talking circuit and then by selecting and outputting it. CONSTITUTION:One of sound IN, dial tone DT and no-tone NT including an input signal from a time-division channel is selected by selecting circuit SEL-IN on the basis of control information from a processor and then supplied to conference talking circuits CF0 and CF1. Further, one of a selective input to them, the outputs of conference talking circuits and no-tone NT selected by selecting circuit SEL-OUT and outputted. As a result, the efficiency of the utilization of a highway is improved and a variety of services can be offered without lowering the multiplicity of a trunk unit.

12. 发明专利

JPS56166690A MULTIFREQUENCY SIGNAL RECEIVER 失效
公开(公告)号：JPS56166690A
公开(公告)日：1981-12-21
申请号：JP6991880
申请日：1980-05-26
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： SHIMOE TOSHIO , IMAGAWA HITOSHI , MARUYAMA KAZUHIRO , FUKUI AKIRA , HIROSE KAZUTO
IPC分类号： H04Q1/457 , H04L27/26 , H04Q1/453
摘要： PURPOSE:To simplify the constitution of a receiver by modulating multifrequency signal to make respective frequency components identical through detecting respective frequencies of the multifrequency signal, and then by calculating an output level via a band-pass filter having said frequency as a center frequency. CONSTITUTION:A multifrequency signal from an input terminal 1 is inputted to detecting circuits 2a-2n which correspond to its respective frequencies and their outputs are modulated by modulating circuits 3a-3n to make identical the frequencies of respective frequency components. The outputs of those modulating circuits 3a-3n are applied to band-pass filters 4a-4n whose center frequencies are equal and their outputs are squared by output level calculation parts 5a-5n to discriminate an output level. The outputs of those detecting circuits 2a-2n are inputted to an output logical circuit 6, and the outputs of the calculation parts 5a-5n are logically processed to discriminate a dial number, control signal, etc., of the multifrequency signal.

13. 发明专利

JPS5675790A DIAL PULSE RECEIVER 失效
公开(公告)号：JPS5675790A
公开(公告)日：1981-06-23
申请号：JP15352479
申请日：1979-11-26
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： IMAGAWA HITOSHI , HASHIZUME YUKINAO , HASEGAWA KOUICHI , OBARA SUSUMU , SHIMOE TOSHIO
IPC分类号： H04Q3/545 , H04Q1/32
摘要： PURPOSE:To reduce the amount of software, by counting dial pulses, detection of abondoned said pulses on its half-way and discrimination an inter-digit by means of logic circuit and memory. CONSTITUTION:A dial pulse count logic circuit 2 references an ACT memory 3 which indicates the effectiveness of receiver during the reception of numerals, LL memory 4 storing the result of scanning before one period of signal bit, dial counter memory 9, and AP memory 12 storing the detection of pulse to detect the part between digits of the dial pulse signals, and performs the detection and count of the dial pulses. A discrimination circuit for abondonment on its way DET15 references an APLL memory 16 storing the result of the AP memory 12 before one period, memory 16 and memory 19 displaying the detection of one numeral, memory 21 storing the numeral, and memory 23 storing the information of the discrimination of abondonment on half way, to discriminate the part inter-digit and the abondonment of half way.

14. 发明专利

JPS5643858A DIGITAL CONFERENCE TELEPHONE SYSTEM 失效
公开(公告)号：JPS5643858A
公开(公告)日：1981-04-22
申请号：JP11950879
申请日：1979-09-17
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , OKI ELECTRIC IND CO LTD , FUJITSU LTD
发明人： SHIRASAWA SUSUMU , KIKUCHI SHIROU , SAKURAI KOUJIROU , KUMASHIRO TADAHIKO , SHIMOE TOSHIO
IPC分类号： H04M3/56 , H04Q11/04
摘要： PURPOSE:To realize a digital conference telephone system with a light load on software processing by preparing time slots of digital conference telephone highways as many as a maximum number of simultaneous speakers as one unit and by inserting PCM codes into empty time slots. CONSTITUTION:The output of telephone set 1 is connected to multiplexer 3, multiplexing digital signals, by way of subscriber's circuit 2 having functions of speech current supply, two-wire/four-wire conversion, PCM coding, etc. The output of multiplexer 3 is led to time-division channel unit 5, which is connected to digital conference trunk 8 via digital conference trunk highways 6 and 7 and at the trunk, voices of subscribers speaking simultaneously are mixed or selected. Time slots on highways 6 and 7 are provided as many as a maximum number of speakers as a unit and when unused time slots appear, PCM codes, etc., that correspond to analog signals of about zero levels are inserted. The output of trunk 8 is led to telephone set 1 via demultiplexer 9.

15. 发明专利

JPS6072363A STEP-OUT DETECTING SYSTEM 失效
公开(公告)号：JPS6072363A
公开(公告)日：1985-04-24
申请号：JP17828183
申请日：1983-09-28
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： GOUHARA SHINOBU , NISHIMURA KAZUO , ARAGAKI NAOYA , TAKAHASHI TATSUROU , SHIMOE TOSHIO
IPC分类号： H04L7/00 , H04J3/06 , H04M3/22 , H04Q11/04
摘要： PURPOSE:To reduce load of processing of soft ware required for step-out detection of a digital subscriber's line by detecting a digital subscriber's line in which step-out is occurred by hardware in a speech path equipment and reporting to software. CONSTITUTION:Synchronous state is monitored for each digital subscriber's line 40 by a synchronous state monitoring circuit 50. Sampling is made at a fixed period for the monitoring output, and when step-out state is detected specified number of times, a step-out detecting circuit 60 decides and detects this as step- out. Last look of the detection output is stored in a step-out storing circuit 70. A step-out event detecting circuit 80 is provided with a step-out event detecting circuit 80 that detect change from normal state of synchronism to step-out state by output of a synchronism storing circuit and the circuit 60 and a hard cue 90 input of which is controlled by the output. Step-out information of the subscriber's line 40 is reported to the controlling device and soft ware through the cue 90.

16. 发明专利

JPS6074795A SIGNAL RECEPTION CIRCUIT 失效
公开(公告)号：JPS6074795A
公开(公告)日：1985-04-27
申请号：JP18069883
申请日：1983-09-30
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： SHIMOE TOSHIO , TAKAHASHI TATSUROU , ARAGAKI NAOYA , GOUHARA SHINOBU
IPC分类号： H04Q1/20 , H04M3/24
摘要： PURPOSE:To prevent malfunction and to attain reduction of time for inservice processing by inhibiting the signal reception at the transient state of state transition of a call processing section in a digital signal processing circuit of an exchange. CONSTITUTION:A 2-input OR gate 12 and a selector 13 to write a low level at inactivating are added. Thus, a last look memory 7 is not revised at write to a hard Q memory 5 and the write of an identical signal from the (N+3)th frame and succeeding frames is suppressed by the write of an active memory 8. Moreover, a processing section reads this signal and performs the revision of the last look memory 7 and activation of the active memory 8 at the state transition. The in-service processing for duplicated running is realized by a simultaneous write order of the last look memory 7 and the active memory 8 from the call processing section.

17. 发明专利

JPS6072345A SYSTEM FOR SYNCHRONIZING PHASE OF DIGITAL SIGNAL 失效
公开(公告)号：JPS6072345A
公开(公告)日：1985-04-24
申请号：JP17828383
申请日：1983-09-28
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： SAKAKIDA HISAHIRO , NAGAI NAOFUMI , SHIMOE TOSHIO
IPC分类号： H04L7/033
摘要： PURPOSE:To make the jitter of a clock zero when no frequency lag occurs, by treating the phase of digital signals in such a way that when the difference between input and output phases is within one pulse of a clock pulse the phases are treated as under a synchronous condition and no phase correcting signal is outputted. CONSTITUTION:A clock Q in which the phase is delayed is obtained by dividing 3 the output of an oscillator 5 into N parts and using a frequency which is almost same as the frequency of an input signal as an output clock P, and then, shifting the clock P by one pulse after giving to a shift register 4. Phases of the clocks P and Q are compared 1 with each other. An up-down counter 2 counts the number of signals which are under a led and delayed conditions only in accordance with the compared result and, when the counted number reaches a previously set value, phase correction is performed. As a result, when the difference between input and output phases is within the one pulse of the clock pulse, they are treated as under a synchronous condition and no phase correcting signals is outputted.

18. 发明专利

JPS5842356A POWER SUPPLY SYSTEM FOR TERMINAL CONTROLLER 失效
公开(公告)号：JPS5842356A
公开(公告)日：1983-03-11
申请号：JP13949881
申请日：1981-09-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SHIMOE TOSHIO , INOUE YOSHIAKI , YAMASHITA HIROYUKI , NAKANO YOSHIO , NAGAI NAOFUMI , SHIMOHARA KATSUNORI
IPC分类号： H04M11/00 , H04M19/00
摘要： PURPOSE:To eliminate the need for a switching circuit and to unify the power supply system, by supplying a logical sum of outputs of power supply devices corresponding to main trunks operated with an intra-office power supply and supplying the power supply to a common part of a terminal controller and extensions, when the main trunks are connected. CONSTITUTION:Digitalized main trunks CL1 and CL2 and a plurality of extensions EX1 and EX2 are accommodated in a terminal controller II, and DC-DC converters CONV1 and CONV2 operated with an intra-office power supply applied via a main trunkIand provided for the controller II when the main trunks CL1 and CL2 are connected. Power is supplied to sections L1 and L2 corresponding to the main trunks with the converters CONV1 and CONV2. Diodes D1 and D2 are connected to the converters CONV1 and CONV2 and a common part C of the device II is provided with a signal processing section SPR. The outputs of the converters CONV1 and CONV2 are ORed and power is supplied to the common part C and the extensions EX1 and EX2 of the device II, allowing to simplify the constitution of the power supply circuits.

19. 发明专利

JP2001016671A SLAVE SYNCHRONIZATION DEVICE 失效
公开(公告)号：JP2001016671A
公开(公告)日：2001-01-19
申请号：JP18180999
申请日：1999-06-28
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SHIMOE TOSHIO , KATAKURA HITOSHI , DOI YUKIHIRO
IPC分类号： H04J3/06 , H04L7/00 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To enable a salve synchronization device replaceable by a DCS(digital clock supply device) to attain a slave synchronization at a low cost with high accuracy in a slave station adopting a slave synchronization system. SOLUTION: This slave synchronization device is provided with a clock monitor means 11 that detects a start point on a time base to which a reference clock synchronously with a transmission line is given, a high speed clock generating means 12 that is synchronously with the reference clock and generates a high-speed clock whose frequency is higher than the frequency of the reference clock, and a frequency synthesis means 13 that applies direct frequency synthesis processing to the high-speed clock to generate a clock to be supplied devices in a station and transmits the generated clock to a confounding path. Then the frequency synthesis means 13 has a frequency divider means 13a that conducts frequency division processing and is provided with an initializing means 14 that initializes the frequency divider means 13a synchronously with either of a front edge or a tail end edge of the clock received from an opposite system via the confounding path for a predetermined period in succession to the start point detected by the clock monitor means 11.

20. 发明专利

JPH04281641A SWITCH CONTROL SYSTEM 失效
公开(公告)号：JPH04281641A
公开(公告)日：1992-10-07
申请号：JP4503791
申请日：1991-03-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SHINOMIYA TOMOHIRO , SHIMOE TOSHIO , TAKEO HIROSHI
IPC分类号： H04Q3/52 , H04J3/16 , H04J3/24 , H04L12/931 , H04L12/951
摘要： PURPOSE:To output a data in the order of arrival by switching the data to an output port while taking the order of input presence signals set when the data reaches an input port into account. CONSTITUTION:Data from plural input ports 1 are stored in respective memories 3 and when the data reach the memory 3, the memory 3 informs an input presence signal IP to an output port output control section 8. The output port output control section 8 arranges the input presence signal noticed when the data from each input port is stored in the relevant memory 3 sequentially, controls a multiplexer 25 so that the data is outputted to the output port 2 in the order of the signal IP when the data is outputted to the output port 2 succeedingly. Thus, the data from the plural input port 1 is outputted to the output port 2 in the order of first-come and the undesired residence of the data is prevented.

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