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11. 发明专利

JPS6355225B2 失效
公开(公告)号：JPS6355225B2
公开(公告)日：1988-11-01
申请号：JP22102383
申请日：1983-11-24
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI , KURODA SHIGERU
IPC分类号： H01L29/812 , H01L21/338 , H01L29/41 , H01L29/417 , H01L29/778 , H01L29/80

12. 发明专利

JPS6354230B2 失效
公开(公告)号：JPS6354230B2
公开(公告)日：1988-10-27
申请号：JP7765581
申请日：1981-05-22
申请人： FUJITSU LTD
发明人： HYAMIZU SUKEHISA , MIMURA TAKASHI
IPC分类号： H01L29/80 , H01L21/331 , H01L21/338 , H01L27/06 , H01L27/08 , H01L29/205 , H01L29/73 , H01L29/778 , H01L29/812

13. 发明专利

JPS63222416A MANUFACTURE OF EPITAXIAL CRYSTAL 失效
公开(公告)号：JPS63222416A
公开(公告)日：1988-09-16
申请号：JP5515487
申请日：1987-03-12
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI , SAITO JUNJI , KURODA SHIGERU
IPC分类号： H01L21/302 , H01L21/20 , H01L21/203 , H01L21/26 , H01L21/3065
摘要： PURPOSE:To prevent damage to a substrate crystal, by exposing the substrate crystal, removing carbon contaminant, covering the crystal with a plasma oxide film, evaporating the plasma oxide film, growing an epitaxial crystal, and obtaining a high quality interface. CONSTITUTION:A substrate crystal is exposed to oxygen plasma, and carbon contaminant is removed. The surface is covered with a plasma oxide film. The substrate crystal is set in a growing chamber. After the plasma oxide film is evaporated, an epitaxial crystal is grown. Then the carbon contaminant, which is put in the interface of the epitaxial crystal/substrate crystal, is extremely reduced. Thus, the high quality interface is obtained, and damage to the substrate crystal is prevented.

14. 发明专利

JPS6228592B2 失效
公开(公告)号：JPS6228592B2
公开(公告)日：1987-06-22
申请号：JP8767079
申请日：1979-07-11
申请人： FUJITSU LTD
发明人： YOKOYAMA NAOKI , MIMURA TAKASHI
IPC分类号： H01L21/306 , H01L21/338 , H01L29/80 , H01L29/812

15. 发明专利

JPS62134978A MANUFACTURE OF COMPLEMENTARY HIGH SPEED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62134978A
公开(公告)日：1987-06-18
申请号：JP27520885
申请日：1985-12-09
申请人： FUJITSU LTD
发明人： KURODA SHIGERU , MIMURA TAKASHI
IPC分类号： H01L29/812 , H01L21/265 , H01L21/338 , H01L29/778 , H01L29/80
摘要： PURPOSE:To prevent a regrown boundary from deteriorating and to form a preferably hetero junction by growing a non-doped compound semiconductor carrier supplying region forming layer on a substrate, then masklessly ion implanting to form a P-type hole supplying region and an N-type electron supplying region, and growing a non-doped compound semiconductor channel layer, thereby completing a planar type. CONSTITUTION:A semi-insulating GaAs substrate 1 is set on an MBE device, a non-doped AlXGa1-XAs carrier supplying region forming layer 2 is grown on the substrate, fed into a substrate 1 maskless ion implanting device to implant P-type impurity ions such as Mg ions or Be ions into a P-channel HEMT forming region to form a P-type hole supplying region 3, and N-type impurity ions such as Si ions are implanted into N-channel HEMT forming region to form an N-type electron supplying region 4. The substrate 1 is again returned to the MBE device, set, and a non-doped GaAS channel layer 5 is grown on the layer 2.

16. 发明专利

JPS62134923A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62134923A
公开(公告)日：1987-06-18
申请号：JP27520985
申请日：1985-12-09
申请人： FUJITSU LTD
发明人： KURODA SHIGERU , MIMURA TAKASHI
IPC分类号： H01L29/68 , H01L21/203 , H01L21/26 , H01L21/265 , H01L21/331 , H01L21/338 , H01L29/20 , H01L29/72 , H01L29/73 , H01L29/737 , H01L29/778 , H01L29/80 , H01L29/812
摘要： PURPOSE:To form easily a thin active layer having a sharp profile of impurity density, the thickness of which is controlled with high accuracy, by implanting ion into the surface of a semiconductor layer to form a layer of high resistivity, on which a thin undoped semiconductor layer is grown by epitaxy, and obtaining an active layer by implanting ion into the undoped semiconductor layer. CONSTITUTION:A GaAs substrate 1 is set in an ion implantation apparatus, and oxygen ion and the like is implanted to form a layer 2 of high resistivity by applying an implantation method. The GaAs substrate 1 is transferred into an MBE apparatus through a vacuumized conveyer and set therein. An undoped AlGaAs layer 3 is grown by applying an MBE method. The GaAs substrate 1 is transferred back to the ion implantation apparatus through the vacuumized conveyer and set therein. Then, silicon ion and the like is implanted by applying the ion implantation method. Thermal treatment is performed to activate impurity, and an N-type AlGaAs active layer 3 whose thickness is precisely controlled is obtained, thereby.

17. 发明专利

JPS6199380A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS6199380A
公开(公告)日：1986-05-17
申请号：JP22150484
申请日：1984-10-22
申请人： Fujitsu Ltd
发明人： SUZUKI MASAHISA , TSUNENOBU KAZUKIYO , MIMURA TAKASHI
IPC分类号： H01L29/812 , H01L21/338 , H01L29/423 , H01L29/778
CPC分类号： H01L29/42316
摘要： PURPOSE:To enhance the reliability of an element, by covering the side wall of the one side of a recess, exposing a part of a first gallium arsenide layer at the bottom surface of the recess, forming a gate electrode, and reducing source resistance. CONSTITUTION:On a GaAs substrate 1, the following parts are sequentially and continuously grown: an undoped GaAs layer 2 as a two-dimensional electron gas feeding layer, a first n-AlGaAs layer 3 as a two-dimensional electron gas feeding layer, a first n-GaAs layer 4 as a cap layer, a second n-AlGaAs layer 9 and a second n-GaAs layer 10. Then, AuGe/Au are sequentially evaporated and a source electrode 5 and a drain electrode 6 are formed. Thereafter, resist 7 is applied on the entire surface of the substrate. After patterning, a hole for a gate forming region is provided. With the remaining resist 7 as a mask, anisotropic etching in the vertical direction with respect to the n-GaAs layer 10 is performed until the n-AlGaAs layer 9 is exposed. Thus a recess is formed. The n-AlGaAs layer 9 is removed by selective wet etching. Al is evaporated obliquely so that the Al is hooked on the source side of the recess. The resist is lifted off, and the Al other tan in the gate region is removed. Thus a gate electrode 8 is formed.
摘要翻译：目的：为了提高元件的可靠性，通过覆盖凹部的一侧的侧壁，在凹部的底表面暴露第一砷化镓层的一部分，形成栅电极，并降低源电阻。构成：在GaAs衬底1上，依次并连续地生长以下部分：作为二维电子气体供给层的未掺杂的GaAs层2，作为二维电子供体层的第一n-AlGaAs层3，第一n-GaAs层4作为覆盖层，第二n-AlGaAs层9和第二n-GaAs层10.然后，AuGe / Au依次蒸发，形成源电极5和漏电极6。此后，将抗蚀剂7施加在基板的整个表面上。在图案化之后，提供用于栅极形成区域的孔。在剩余的抗蚀剂7作为掩模的情况下，进行相对于n-GaAs层10的垂直方向的各向异性蚀刻直到n-AlGaAs层9露出。因此形成凹部。通过选择性湿蚀刻除去n-AlGaAs层9。 Al倾斜地蒸发，使得Al钩在凹部的源侧。抗蚀剂被剥离，并且除去栅极区域中的Al另外的tan。因此形成栅电极8。

18. 发明专利

JPS6124265A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS6124265A
公开(公告)日：1986-02-01
申请号：JP14436784
申请日：1984-07-13
申请人： Fujitsu Ltd
发明人： SUZUKI MASAHISA , MIMURA TAKASHI
IPC分类号： H01L29/812 , H01L21/338 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L27/095 , H01L29/778
CPC分类号： H01L27/0605
摘要： PURPOSE:To simultaneously form the gate of both E/D transistors by one mask process precisely and to enable accurately controlling the threshold voltage of each enhancement type transistor and depletion type transistor by such a method as a specific process in the manufacture of the gate. CONSTITUTION:The first and the second semiconductor layers 22, 23 for a channel layer and a carrier supply layer, the third and the fourth semiconductor layers 24, 25 for the threshold voltage control layer and the etching stop layer of a depletion type transistor (D) and the fifth semiconductor layer 26 which enables ohmic contact are grown on a substrate 21. Then, an insulation film 27 is formed on all the surface, the insulation film 27 of a region where an enhancement type transistor (E) is to be formed is selectively removed and a depression which reaches to the fourth semiconductor layer 25 at (E) region for forming a gate electrode is formed. Then, the extension of the above-mentioned depression at (E) region reaching to the surface of the second semiconductor layer 23 and the formation of the depression for forming the gate electrode reaching to the surface of the fourth semiconductor layer 25 at (D) region are simultaneously carried out.
摘要翻译：目的：通过一个掩模处理精确地同时形成两个E / D晶体管的栅极，并且能够通过栅极制造中的具体工艺的方法来精确地控制每个增强型晶体管和耗尽型晶体管的阈值电压。构成：用于沟道层和载流子供应层的第一和第二半导体层22,23，用于阈值电压控制层的第三和第四半导体层24,25以及耗尽型晶体管（D）的蚀刻停止层）和能够欧姆接触的第五半导体层26生长在基板21上。然后，在所有表面上形成绝缘膜27，形成增强型晶体管（E）的区域的绝缘膜27 并且形成在用于形成栅电极的（E）区域到达第四半导体层25的凹陷。然后，在（D）的（D）到达第四半导体层25的表面的（E）区域的上述凹陷的延伸到达第二半导体层23的表面，形成用于形成栅电极的凹陷，区域同时进行。

19. 发明专利

JPS6048909B2 失效
公开(公告)号：JPS6048909B2
公开(公告)日：1985-10-30
申请号：JP8206781
申请日：1981-05-29
申请人： FUJITSU LTD
发明人： MIMURA TAKASHI
IPC分类号： H01L29/205 , H01L21/33 , H01L21/331 , H01L21/338 , H01L29/70 , H01L29/73 , H01L29/76 , H01L29/778 , H01L29/812

20. 发明专利

JPS60206074A FIELD EFFECT TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60206074A
公开(公告)日：1985-10-17
申请号：JP6094484
申请日：1984-03-30
申请人： FUJITSU LTD
发明人： SUZUKI MASAHISA , MIMURA TAKASHI
IPC分类号： H01L29/812 , H01L21/338 , H01L29/205 , H01L29/417 , H01L29/778
摘要： PURPOSE:To contrive the reduction of leakage current flowing from source to gate via electrode contact layer by a method wherein an n type electron supply layer is provided with an n type electrode contact layer with a smaller dopant concentration than that of this layer. CONSTITUTION:A non-doped GaAs active layer 2, the n type AlGaAs electron supply layer 3, the n type GaAs electrode contact layer 4, a source electrode 5, a gate electrode 6, and a drain electrode 7 are formed on a semi-insulation GaAs substrate 1. Here, if the dopant concentration in the layer 3 is ND1 and that in the layer 4 is ND2, ND1>ND2. As a result, a depletion layer 9 stretching out of the junction between the electrode 6 and the layer 4 toward the layer 4 becomes thicker, and a leakage current 11 passing through the layer 4 is inhibited satisfactorily, resulting in the suppression of voltage drop in this part. Thereby, an effective field can be impressed from the electrode 6 on a high-resistant layer 2 where a two-dimensional electron gas layer 8 is to be formed. Therefore, the gate withstand voltage improves because of the reduction of the current 11. Besides, the mutual conductance improves.

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