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    • 14. 发明专利
    • PLL OSCILLATION CIRCUIT
    • JPH10285027A
    • 1998-10-23
    • JP10102297
    • 1997-04-03
    • SONY TEKTRONIX CORP
    • SATO YASUSHI
    • H03L7/197H01P7/04H03H11/40
    • PROBLEM TO BE SOLVED: To allow the circuit to generate a fractional frequency signal while realizing a shorter lock-in time. SOLUTION: A reference signal generating circuit 10 employs a crystal oscillator to generate a reference signal with a reference frequency. A reference signal frequency divider circuit 21 frequency-divides the reference signal to produce a frequency division reference signal Fdr. A VCO 18 has a 1st frequency control circuit 17 and a frequency of an output signal of the VCO 18 is controlled in response to a control voltage applies to the circuit 17. A phase comparator circuit 12 produces a control voltage in response to a phase difference between a phase of a reference frequency Fr and a comparison frequency Fp outputted from a frequency divider circuit 20. An SSB mixer 30 mixers the output signal of the VCO 18 with the frequency division reference signal to produce a mixed signal. A coaxial dielectric filter DRF 16 passes only a desired frequency component of the mixed signal because its pass frequency band is controlled in response to a control voltage applied to its 2nd frequency control circuit 15. An offset circuit 11 produces an offset between control voltages to be respectively applied to the 1st and frequency control circuits 17, 15 in response to the frequency of the frequency division reference signal.
    • 17. 发明专利
    • POWER SUPPLY APPARATUS
    • JPH1023663A
    • 1998-01-23
    • JP18889696
    • 1996-06-28
    • SONY TEKTRONIX CORP
    • ENDO SUSUMUMUROFUSHI TATSUYAKATO KATSUHISA
    • G01R31/12H02J1/00
    • PROBLEM TO BE SOLVED: To supply a power with little noise by a method, wherein a required number of capacitors are connected, so as to form a matrix of (i) columns and (k) rows and the range of the output voltage of a charging means is controlled, in accordance with the column number (i). SOLUTION: One or more ranges of the output voltage of a 1st capacitor bank 14 are provided and a row number (k), i.e., the number of capacitors which are connected in parallel to each other, is switched in accordance with the range. Specifically, the higher the voltage of the range, the smaller the number (k) of the rows. Although a current or a voltage with little droop can be outputted, when the row number (k) is large, as the charging value is large when the output voltage of the 1st capacitor bank is high, a current or a voltage with relatively little droop can be outputted, even if the number of capacitors connected in parallel to each other is small. With this constitution, the total number of capacitors of which the 1st capacitor bank 14 consists is not changed within the range of allowable drooping, even if the range of the output voltage is changed.
    • 18. 发明专利
    • EQUIPMENT AND METHOD FOR DISPLAYING WAVEFORM
    • JPH1019937A
    • 1998-01-23
    • JP19574296
    • 1996-07-05
    • SONY TEKTRONIX CORP
    • KITAGAWA TAKESHI
    • G01R13/20
    • PROBLEM TO BE SOLVED: To provide equipment and a method for displaying a waveform which enable natural display of the waveform on the basis of a digital waveform data sequence without impairing a property of real time, although they have inexpensive constitution not necessitating an interpolation processing. SOLUTION: This equipment for display has a waveform data sequence reproducing means 18 which generates reproduced digital waveform data sequences sequentially so that a data point of the reproduced waveform data sequence of each cycle may correspond to a time point different from the one to which the data point of the reproduced waveform data sequence of another cycle corresponds, on an equivalent time base, a pixel address generating means 20 which receives the reproduced waveform data sequence and generates a reproduced pixel address, a pixel address accumulating means 22 which accumulates the reproduced pixel address for each pixel in accordance with the reproduced pixel address received from the pixel address generating means 20 and a display control means 24 which regulates display properties of a corresponding pixel in accordance with an accumulated value of each pixel obtained by the pixel address accumulating means 22.
    • 19. 发明专利
    • METHOD FOR DISCRIMINATING AND DISPLAYING DIGITAL PHASE MODULATING SYSTEM
    • JPH09298567A
    • 1997-11-18
    • JP13281796
    • 1996-04-30
    • SONY TEKTRONIX CORP
    • OSHIRODA HIDEAKI
    • H04L27/38H04L27/18H04L27/227
    • PROBLEM TO BE SOLVED: To exactly discriminate the digital phase modulating system of an input signal from unknown radio equipment by finding an estimated carrier frequency from the frequency area data of an unknown digital phase modulated signal, detecting that frequency, operating it, finding the symbol point of phase modulation and displaying data provided by detecting and operating that frequency again. SOLUTION: A down converter 12 converts the radio wave of unknown radio equipment received by an antenna 10 to an intermediate frequency signal and a data spectrum analyzer 14 converts that signal to digital frequency component data and stores them in a memory. Afterwards, a computer 16 finds the estimated carrier frequency from the digital frequency component data in the memory and finds an orthogonal coordinate by detecting and operating time area data based on this frequency. Further, the symbol point of phase modulation is found at the respective points of these coordinate data and a true carrier frequency is found from this symbol point. Then, the time area data are detected and operated again based on the found carrier frequency and the provided symbol point is displayed on a coordinate plane.