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111. 发明专利

JP2014015490A Encapsulation resin sheet, manufacturing method of electronic component package, and electronic component package 有权
标题翻译：电子元件封装的制造树脂片，电子元器件包装的制造方法
公开(公告)号：JP2014015490A
公开(公告)日：2014-01-30
申请号：JP2012151557
申请日：2012-07-05
申请人： Nitto Denko Corp , 日東電工株式会社
发明人： TOYODA HIDESHI , SHIMIZU YUSAKU
IPC分类号： C08J5/18 , H01L21/56 , H01L23/29 , H01L23/31
CPC分类号： H01L21/56 , H01L23/29 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/3511 , Y10T428/24355 , H01L2224/83 , H01L2224/81 , H01L2224/11 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an encapsulation resin sheet capable of obtaining a clean, smooth and flat ground surface by grinding after resin encapsulation, and to provide a manufacturing method of an electronic component package using the same, and an electronic component package obtained by the manufacturing method.SOLUTION: In an encapsulation resin sheet, after thermosetting treatment at 180°C for an hour and then having ground under a condition at 1000 m/min of a peripheral speed of a grinding tool, 100 μm feed pitch, and 10 μm cut-in depth, average surface roughness Ra of a ground surface is 1 μm or smaller, and Shore D hardness at 100°C after the thermosetting treatment is 70 or higher.
摘要翻译：要解决的问题：提供一种能够在树脂封装之后通过研磨获得清洁，平滑和平坦的地面的封装树脂片材，并提供使用其的电子部件封装的制造方法以及由制造方法。在密封树脂片中，在180℃下热处理1小时后，在研磨工具的圆周速度1000m / min的条件下进行研磨，进料间距为100μm，进料间距为10 μm切入深度，研磨面的平均表面粗糙度Ra为1μm以下，热硬化处理后的100℃下的肖氏D硬度为70以上。

112. 发明专利

JP5378380B2 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：JP5378380B2
公开(公告)日：2013-12-25
申请号：JP2010521728
申请日：2009-07-23
申请人：ルネサスエレクトロニクス株式会社
发明人：健太郎森 , 秀哉村井 , 新太郎山道 , 連也川野 , 康志副島
IPC分类号： H05K3/46 , H01L23/12 , H01L23/36
CPC分类号： H05K1/185 , H01L23/5389 , H01L24/19 , H01L2224/04105 , H01L2224/20 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01058 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H05K1/115 , H05K3/4644 , H05K2201/0352 , H05K2201/10674 , H05K2203/0152 , H05K2203/0156 , H05K2203/063 , H05K2203/1469 , H01L2924/00
摘要： A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers.

113. 发明专利

JP5340789B2 Electronic device and a method of manufacturing the same 有权
公开(公告)号：JP5340789B2
公开(公告)日：2013-11-13
申请号：JP2009091956
申请日：2009-04-06
申请人：新光電気工業株式会社
发明人：健太内山
IPC分类号： H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L23/5389 , H01L21/486 , H01L21/565 , H01L21/568 , H01L23/3121 , H01L23/3128 , H01L23/49827 , H01L24/19 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/96 , H01L25/0652 , H01L2224/04105 , H01L2224/16225 , H01L2224/24137 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73267 , H01L2224/82039 , H01L2224/92244 , H01L2225/06524 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/15788 , H01L2924/181 , H01L2924/18162 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： An electronic device includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first electronic component, a first sealing resin, and a first multilayer interconnection structure including a first interconnection pattern directly connected to a first electrode pad of the first electronic component. The second semiconductor device includes a second electronic component, a second sealing resin, and a second multilayer interconnection structure including a second interconnection pattern directly connected to a second electrode pad of the second electronic component. The first semiconductor device is stacked on and bonded to the second semiconductor device through an adhesive layer with the first multilayer interconnection structure of the first semiconductor device facing toward the second sealing resin of the second semiconductor device. The first interconnection pattern and the second interconnection pattern are connected through a through electrode provided through the adhesive layer and the second sealing resin.

115. 发明专利

JP5313305B2 A method of manufacturing the layered chip package 有权
公开(公告)号：JP5313305B2
公开(公告)日：2013-10-09
申请号：JP2011149245
申请日：2011-07-05
申请人：ヘッドウェイテクノロジーズインコーポレイテッド , 新科實業有限公司SAE Magnetics(H.K.)Ltd.
发明人：芳高佐々木 , 浩幸伊藤 , 寛池島 , 淳飯島
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/50 , H01L23/49805 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/24137 , H01L2225/06513 , H01L2225/06551 , H01L2225/06565 , H01L2924/07802 , H01L2924/18162 , H01L2924/00
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.

116. 发明专利

JP5258838B2 Semiconductor device 有权
公开(公告)号：JP5258838B2
公开(公告)日：2013-08-07
申请号：JP2010113899
申请日：2010-05-18
申请人：株式会社東芝
发明人：田敦子飯 , 豊小野塚 , 谷和彦板
IPC分类号： H01L25/16 , H01L23/29 , H01L23/31
CPC分类号： H01L24/96 , H01L21/568 , H01L23/295 , H01L23/3135 , H01L2224/04105 , H01L2224/18 , H01L2224/24137 , H01L2224/24195 , H01L2924/10253 , H01L2924/1461 , H01L2924/15788 , H01L2924/18162 , H01L2924/3511 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device configured to enable a warp, which may be caused when resin cures, to be suppressed and in addition, a thickness to be reduced. SOLUTION: The semiconductor device comprises a stacked structure having: a first chip 20; a second chip 10; and a first adhesive film 32a including a first resin 34 to which a first material-constant adjusting agent 36a is added, and a second adhesive film 32b including a second resin 34 to which a second material-constant adjusting agent 36a is added; arranged in a stacked configuration. In this semiconductor device, there is provided a bonding section 30 adapted to bond at least the side face of the first chip and a side face of the second chip. The first resin and the second resin are of the same material, the first material-constant adjusting agent and the second material-constant adjusting agent are substantially the same in average grain diameters while an added amount of the first material-constant adjusting agent that is added to the first adhesive film differs from that of the second material-constant adjusting agent that is added to the second adhesive film. COPYRIGHT: (C)2010,JPO&INPIT

117. 发明专利

JP2013098373A Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2013098373A
公开(公告)日：2013-05-20
申请号：JP2011240125
申请日：2011-11-01
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SASAKI SHINYA , TANI MOTOAKI
IPC分类号： H01L23/12
CPC分类号： H01L24/96 , H01L21/568 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/19 , H01L2225/1035 , H01L2225/1058 , H01L2924/18162 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To solve the problem that wear of a front end part of a drill cannot be avoided when the drill is used to form a through hole in a support base including much of inorganic filler.SOLUTION: A reconfigured wafer is constituted of semiconductor chips and a support base made of insulating resin, which is fixed to the semiconductor chips and is disposed up to the outside of edges of the semiconductor chips. A rewiring layer is formed on a first surface being one surface of the reconfigured wafer. The rewiring layer includes an insulating film made of insulating resin, a plurality of wires arranged in the insulating film, a plurality of first metallic pads arranged in positions not overlapping with the semiconductor chips within the insulating film, and a plurality of second metallic pads exposed to a surface of the insulating film. Through holes reaching the first pads through the support base are formed from a second surface opposite to the first surface of the reconfigured wafer. Conductive vias connected to the first pads are formed in the through holes.
摘要翻译：要解决的问题：为了解决当钻头在包括大量无机填料的支撑基底中形成通孔时不能避免钻头前端部磨损的问题。解决方案：重新配置的晶片由半导体芯片和由绝缘树脂制成的支撑基座构成，其固定到半导体芯片并且设置在半导体芯片的边缘的外侧。再配线层形成在作为重新配置的晶片的一个表面的第一表面上。再布线层包括由绝缘树脂制成的绝缘膜，布置在绝缘膜中的多根布线，布置在绝缘膜内与半导体芯片不重叠的位置的多个第一金属垫，以及多个第二金属垫暴露到绝缘膜的表面。通过支撑基座到达第一焊盘的通孔由与重新配置的晶片的第一表面相对的第二表面形成。连接到第一焊盘的导电通孔形成在通孔中。版权所有（C）2013，JPO＆INPIT

118. 发明专利

JP5175823B2 A method of manufacturing a semiconductor package 有权
公开(公告)号：JP5175823B2
公开(公告)日：2013-04-03
申请号：JP2009243896
申请日：2009-10-22
申请人：新光電気工業株式会社
发明人：健太内山
IPC分类号： H01L23/12
CPC分类号： H01L24/96 , H01L21/568 , H01L2224/12105 , H01L2224/16225 , H01L2224/19 , H01L2224/32225 , H01L2224/73204 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/18162 , H01L2924/00 , H01L2924/00012

119. 发明专利

JP2013507788A Micro-electronics package and a method of manufacturing the same 有权
公开(公告)号：JP2013507788A
公开(公告)日：2013-03-04
申请号：JP2012534202
申请日：2010-09-20
申请人：インテルコーポレイション
发明人：ケイ．ナルラ，ラヴィ , アー．マエス，ホアン , ジェイ．マニュシャロウ，マシュー
IPC分类号： H01L23/12
CPC分类号： H01L24/24 , H01L21/568 , H01L23/3128 , H01L24/16 , H01L24/48 , H01L24/82 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/16225 , H01L2224/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18162 , H01L2924/19107 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要：マイクロエレクトロニクスパッケージは、第１の複数の導電性パッド（２１１）が付着されたダイ（２１０）を有する。マイクロエレクトロニクスパッケージは更に第１の層（２２０）と第２の層（１３０）とを有する。第１の層は、第１の複数の導電性パッドに電気的に接続された第１の複数の導電性ビア（１２１）を有する。第２の層は、当該第２の層の周縁部（１３５）付近に配置された第２の複数の導電性パッド（１３１）と、第１の複数の導電性ビアと第２の複数の導電性パッドとに電気的に接続された複数の導電性トレース（１３２）とを有する。マイクロエレクトロニクスパッケージはまた、各ワイヤボンドが第２の複数の導電性パッドのうちの１つに電気的に接続された複数のワイヤボンド（２４０）を有する。

120. 发明专利

JP2012248916A Manufacturing method of elastic wave device 审中-公开
标题翻译：弹性波装置的制造方法
公开(公告)号：JP2012248916A
公开(公告)日：2012-12-13
申请号：JP2011116552
申请日：2011-05-25
申请人： Taiyo Yuden Co Ltd , 太陽誘電株式会社
发明人： INOUE KAZUNORI , MIYASHITA TSUTOMU , MATSUMOTO KAZUHIRO
IPC分类号： H03H3/08 , H03H9/25
CPC分类号： H01L41/338 , H01L21/568 , H01L24/97 , H01L2224/04105 , H01L2224/11 , H01L2224/12105 , H01L2224/96 , H01L2924/18162 , H03H3/08 , H03H9/0576
摘要： PROBLEM TO BE SOLVED: To simplify the manufacturing process while reducing the manufacturing cost, in the manufacture of an elastic wave device including a plurality of elastic wave filters.SOLUTION: Wafers (11, 21) on which elastic wave devices having different characteristics are formed are divided into stripes, and some of them are moved to other adhesive sheets (60, 70), selectively. The wafers in stripe-shape are aligned alternately on one of the adhesive sheets (60, 70) by matching the adhesive sheets, on which the wafers including the elastic wave devices having different characteristics are pasted selectively, each other. Under this state, the entire resin sealing, formation of through holes, formation of through electrodes, and formation of solder balls are carried out collectively, and the elastic wave devices are individualized by finally dicing the entirety. When compared with a case where piezoelectric substrates(chip) of wafer level package are previously arranged and integrated, the manufacturing process is simplified and the manufacturing cost can be reduced.
摘要翻译：要解决的问题：为了简化制造过程，同时降低制造成本，在制造包括多个弹性波滤波器的弹性波装置时。解决方案：其上形成有不同特性的弹性波器件的晶片（11,21）被分成条纹，并且其中一些被选择性地移动到其它粘合片（60,70）。通过使包含具有不同特性的弹性波装置的晶片的晶片彼此粘合在一起，粘合片（60,70）之间交替地对准条形状的晶片。在这种状态下，集体进行整个树脂密封，通孔的形成，通孔的形成和焊球的形成，并且通过最终切割整体来使弹性波器件个体化。与晶片级封装的压电基板（芯片）预先布置并集成的情况相比，制造工艺简化，并且可以降低制造成本。版权所有（C）2013，JPO＆INPIT

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