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101. 发明专利

JP2007180076A Multilayer printed circuit board 有权
标题翻译：多层印刷电路板
公开(公告)号：JP2007180076A
公开(公告)日：2007-07-12
申请号：JP2005373733
申请日：2005-12-27
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI
IPC分类号： H05K3/46 , H05K1/18
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2224/16227 , H05K1/113 , H05K1/115 , H05K3/4602 , H05K3/4652 , H05K2201/0352 , H05K2201/09536 , H05K2201/096 , H05K2201/10674 , Y10T29/49139
摘要： PROBLEM TO BE SOLVED: To provide a multilayer printed circuit board which hardly suffers from malfunction by preventing a delay in power supply to a transistor of a processor core of an IC chip mounted thereon. SOLUTION: The multilayer printed circuit board has such a structure that a build-up wiring layer wherein conductor circuits and insulating resin layers are alternately stacked is formed on a core substrate having through-hole conductors, and a mounting portion for mounting a semiconductor element such as an IC is formed in a surface layer of the build-up wiring layer. A pitch in which the through-hole conductors are arranged in a region immediately below a region wherein the semiconductor element such as an IC is to be mounted is set smaller than a pitch in which the through-hole conductors are arranged in other regions. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供几乎不会发生故障的多层印刷电路板，其防止对安装在其上的IC芯片的处理器核心的晶体管的电源的延迟。解决方案：多层印刷电路板具有这样的结构，其中导体电路和绝缘树脂层交替堆叠的堆积布线层形成在具有通孔导体的芯基板上，以及安装部分半导体元件如IC形成在积层布线层的表面层中。通孔导体布置在其中要安装诸如IC的半导体元件的区域的正下方的区域中的间距被设定为小于在其它区域中布置通孔导体的间距。版权所有（C）2007，JPO＆INPIT

102. 发明专利

JP2005191559A Multilayer printed wiring board 有权
标题翻译：多层印刷接线板
公开(公告)号：JP2005191559A
公开(公告)日：2005-07-14
申请号：JP2004350731
申请日：2004-12-03
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , MOCHIDA AKIYOSHI
IPC分类号： H05K1/11 , H05K1/16 , H05K3/46
CPC分类号： H05K1/162 , H05K1/0231 , H05K1/0271 , H05K1/113 , H05K3/4602 , H05K2201/0133 , H05K2201/0175 , H05K2201/0179 , H05K2201/0187 , H05K2201/09509 , H05K2201/09518 , H05K2201/09563 , H05K2201/096 , H05K2201/09718 , H05K2201/09763 , H05K2201/10522 , H05K2201/10734
摘要： PROBLEM TO BE SOLVED: To provide a sufficient decoupling effect to a multilayer printed wiring board that comprises a buildup portion formed by electrically connecting multiple wiring patterns, which are stacked via insulating layers, through via holes in the insulating layers. SOLUTION: A multilayer printed wiring board 10 comprises: a mounting portion 60 having a surface on which a semiconductor element electrically connected to a wiring pattern 32 or the like is mounted; and a laminated capacitor portion 40 having a ceramic high-dielectric layer 43 and first and second laminated electrodes 41 and 42 between which the high-dielectric layer 43 is placed. One of the first and second laminated electrodes 41 and 42 is connected to the power supply line of the semiconductor element, and the other is connected to a ground line. Since the high-dielectric layer 43 of the laminated capacitor portion 40 connected between the power supply line and the ground line in the multilayer printed wiring board is made of ceramic, the capacitance of the laminated capacitor portion 40 can be increased. Accordingly, a sufficient decoupling effect can be obtained even under a condition where instantaneous lowering of potential is likely to occur. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种对多层印刷线路板提供足够的去耦效果，该多层印刷线路板包括通过绝缘层通过电绝缘层堆叠的多个布线图形电连接而形成的积层部分。解决方案：多层印刷线路板10包括：安装部分60，其具有安装有电连接到布线图案32等的半导体元件的表面; 以及具有陶瓷高电介质层43的叠层电容器部分40和放置有高电介质层43的第一和第二叠层电极41和42。第一和第二层压电极41和42中的一个连接到半导体元件的电源线，另一个连接到接地线。由于连接在多层印刷电路板中的电源线和接地线之间的层叠电容器部分40的高电介质层43由陶瓷制成，因此可以增加层叠电容器部分40的电容。因此，即使在可能发生电位瞬间降低的条件下，也可以获得足够的去耦效应。版权所有（C）2005，JPO＆NCIPI

103. 发明专利

JP2005123547A Interposer and multilayer printed wiring board 审中-公开
标题翻译：插件和多层印刷接线板
公开(公告)号：JP2005123547A
公开(公告)日：2005-05-12
申请号：JP2003381047
申请日：2003-11-11
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , FURUYA TOSHIKI
IPC分类号： H01L23/12 , H01L21/60 , H01L23/32
CPC分类号： H01L2224/16225 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To provide an interposer that can prevent the disconnection of a wiring pattern on an IC chip mounted on a package substrate. SOLUTION: The stress caused by the difference between the coefficients of thermal expansion of a multilayer printed wiring board 10 having a large coefficient of thermal expansion and the IC chip 110 having a small coefficient of thermal expansion can be absorbed by interposing the interposer 70 between the package substrate 10 and IC chip 110. Particularly, the stress is absorbed in the interposer 70 by using an insulating substrate having a Young's modulus of 3-40 GPa as the insulating substrate 80 constituting the interposer 70. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以防止安装在封装基板上的IC芯片上的布线图案断开的插入件。解决方案：具有大的热膨胀系数的多层印刷电路板10的热膨胀系数与具有小的热膨胀系数的IC芯片110之间的差异导致的应力可以通过插入插入件特别地，通过使用具有3-40GPa的杨氏模量的绝缘基板作为构成内插器70的绝缘基板80，在中介层70中吸收应力。版权所有：（C）2005，JPO＆NCIPI

104. 发明专利

JP2004023002A Multilayered circuit board and its manufacturing method 有权
公开(公告)号：JP2004023002A
公开(公告)日：2004-01-22
申请号：JP2002179061
申请日：2002-06-19
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , TAMAKI MASANORI
IPC分类号： H05K1/11 , H05K3/46
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a multilayered circuit board exhibiting excellent reliability in electrical connection by improving connectivity between conductive bumps and via holes. SOLUTION: A part of a solder bump 24 is made to creep to the interface of an opening 16 constituting a via hole 18 and copper plating 17. Consequently, adhesion and connection strength can be enhanced between the copper plating 17 forming the via hole and a conductor circuit 28 through the solder bump 24. Although electric resistance is high at the contact interface between different kinds of metal, i.e. solder of the solder bump 24 and copper of the copper plating 17, contact area with the copper plating 17 forming the via hole 18 is increased because the solder bump 24 is made to creep and electric resistance can be decreased between the solder bump 24 and the copper plating 17. COPYRIGHT: (C)2004,JPO

105. 发明专利

JP2004022999A Multilayered circuit board and its producing process 有权
公开(公告)号：JP2004022999A
公开(公告)日：2004-01-22
申请号：JP2002179058
申请日：2002-06-19
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： KARIYA TAKASHI , TAMAKI MASANORI
IPC分类号： H05K1/09 , H05K1/11 , H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayered circuit board exhibiting excellent reliability in electrical connection by improving connectivity between a conductive bump and a conductor circuit. SOLUTION: Each single-sided circuit board A and single-sided circuit boards B1, B2, B3 and B4 are connected electrically by contacting the solder bump 24 and the conductor circuit 28 to each other. A tin film (coating layer) 29 is provided on the surface of the conductor circuit 28 in contact with the solder bump 24. Consequently, local melting of a cell is prevented between the solder bump 24 and the conductor circuit 28 and connection reliability is ensured between them. COPYRIGHT: (C)2004,JPO

106. 发明专利

JP2003218527A MULTILAYERED CIRCUIT BOARD AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003218527A
公开(公告)日：2003-07-31
申请号：JP2002010816
申请日：2002-01-18
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI , SEGAWA HIROSHI , TAMAKI MASANORI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To improve the electrical connectability and connection reliability between one-sided circuit boards in a multilayered circuit board, by suppressing the warping of the whole body of the circuit board at the time of forming the circuit board by laminating the one-sided circuit boards upon another. SOLUTION: The multilayered circuit board is constituted by laminating a plurality of one-sided circuit boards upon another and uniting the circuit boards in one body. Each of the one-sided circuit board has an insulating substrate, a conductor circuit formed on one surface of the substrate, via holes formed by packing a conductive material in openings formed from the other surface of the substrate to the conductor circuit, and conductive bumps electrically connected to the via holes and formed to be protruded to the outsides of the openings. In the multilayered circuit board, the mat-treated surface of metal foil 28 having the mat-treated surface on one side is press-contacted with the conductive bump-side surface of inner one of the laminated one-sided circuit boards. In addition, the foil 28 is formed to a conductor circuit having a prescribed wiring pattern. COPYRIGHT: (C)2003,JPO

107. 发明专利

JP2003218522A MULTILAYER PRINTED-CIRCUIT BOARD AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003218522A
公开(公告)日：2003-07-31
申请号：JP2002010813
申请日：2002-01-18
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI , SEGAWA HIROSHI , TAMAKI MASANORI
IPC分类号： H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To improve electrical connectability and reliability on a connection by inhibiting the generation of the warp of the whole board when a plurality of one-surface circuit boards are laminated and multi-layered. SOLUTION: In a multilayer printed-circuit board in which a plurality of one-sided circuit boards with insulating base materials, conductor circuits 28 formed on one surfaces of the base materials, via holes containing a conductive substance 18 filled into openings reaching the conductor circuits from the other surfaces of the base materials and conductive bumps 44 electrically connected to the via holes and formed to project outside the openings and laminated through adhesive layers and unified, the multilayer printed-circuit board, in which the mat surface of a metallic foil 30, in which one surface is mat-finished, is contact-bonded with a surface on the conductive bump side of either one one-sided circuit board in a plurality of the laminated one-sided circuit boards in the metallic foil 30 and which is formed to the conductor circuits with fixed wiring patterns, and its manufacturing method are proposed. COPYRIGHT: (C)2003,JPO

108. 发明专利

JP2002223069A METHOD FOR MANUFACTURING PRINTED BOARD 失效
公开(公告)号：JP2002223069A
公开(公告)日：2002-08-09
申请号：JP2001016674
申请日：2001-01-25
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI
IPC分类号： H05K3/42 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed board which can securely protect a conductor layer when a via hole is filled and prevent the printed board from deforming. SOLUTION: When the via hole 5 is filled with a plating conductor 7, a reinforcing plate 10 is put covering the entire surface of copper foil 4 across a thermal peeling sheet 11 and a terminal 13 is brought into contact with the copper foil 4 from the side of an insulating substrate 3. Consequently, the surface on the side of the copper foil 4 can completely be sealed with the reinforcing plate 10, so the copper foil 4 is prevented from being contaminated with plating liquid 22. A one-side coppered laminated plate 2 can be reinforced by superposing the reinforcing plate 10 and prevented from deforming during operation. Further, when the terminal 13 is pressed into contact with the copper foil 4, the tip of the terminal 13 can be prevented from breaking through the copper foil 4. Consequently, it is made easy to handle the printed board 1 in a plating process and the operability can be improved.

109. 发明专利

JP2001230549A METHOD FOR MANUFACTURING MULTIL AYER PRINTED WIRING BOARD CIRCUIT BOARD 失效
公开(公告)号：JP2001230549A
公开(公告)日：2001-08-24
申请号：JP2000018171
申请日：2000-01-27
申请人： IBIDEN CO LTD
发明人： KARIYA TAKASHI
IPC分类号： H05K3/40 , H05K1/03 , H05K3/00 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer printed wiring board circuit board which can reduce manufacturing cost and stabilize interlayer connection resistance. SOLUTION: There is formed a non-through hole 18 which reaches a copper foil 12 by conducting a laser irradiation from one face of an insulation base material 10, in which the copper foil 12 is stuck, to the other face. A conductive paste 20 is filled in the non-through hole 18 by vacuum pressure deaerating to form a filling via hole 22, and a resin adhesives layer 14 is provided on an insulation base material 10 on the side of exposing the conductive paste 20. After a copper foil 24 is hot-bonded via the adhesives layer 14, a both-face circuit plate having conductive circuits 26, 28 is manufactured through etching process. Similarly, the copper foil of the insulation base material 10, in which the copper foil 12 is stuck to one face, is etched to form a conductive circuit 34. Laser irradiation is conducted from the other face of the insulation base material 10, to form the non-through hole 18 which reaches the conductor circuit 34. The conductive paste 20 is filled in the non-through hole 18 by vacuum pressure deaeration to form a via hole 22, to manufacture a one-face circuit substrate 40.

110. 发明专利

JP2001217549A MULTILAYER CIRCUIT BOARD 失效
公开(公告)号：JP2001217549A
公开(公告)日：2001-08-10
申请号：JP2000356700
申请日：2000-11-22
申请人： IBIDEN CO LTD
发明人： ASAI MOTOO , KARIYA TAKASHI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer circuit board suited to mother boards which enables the increase of the wiring density and the high density mounting. SOLUTION: The multilayer circuit board has layer resin insulation layers 64, 76 and conductor layers 82 alternately laminated on both surfaces of a multilayer core board 60 having conductor circuits in inner layers, and buildup wiring layers having conductor layers interconnected through vias 70. The multilayer core board 60 is formed by laminating through adhesive layers 64, 76 and heating and pressing an bloc a plurality of circuit boards each having conductor circuits, on one or both surfaces of an insulative hard base and vias composed of a conductive substance filled in holes piercing the insulative hard base to reach the conductor circuits. A solder resist layer 90 covers the surface of the outermost conductor layer of each buildup wiring layer, and at least a part of the conductor layer 82 exposed through openings of the solder resist layer 90 is formed in the form of conductor pads 96 or connecting terminals.

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