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91. 发明专利

JP2008288601A Electrical device 有权
标题翻译：电气设备
公开(公告)号：JP2008288601A
公开(公告)日：2008-11-27
申请号：JP2008136645
申请日：2008-05-26
申请人： Sony Chemical & Information Device Corp , ソニーケミカル&インフォメーションデバイス株式会社
发明人： MATSUSHIMA TAKAYUKI , SAITO MASAO
IPC分类号： H01L21/60 , C09J5/04 , C09J163/00 , G02F1/1345 , H01B13/00
CPC分类号： H01L24/81 , H01L2224/16225 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/83191 , H01L2224/83192 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an electrical device using an adhesive excellent in preserving property and cures quickly at a low temperature. SOLUTION: A first and a second adhesive material have separately a first and a second curing agent, respectively. Since only when the first and the second curing agent start to react, first and second resin components polymerize, the adhesive is not cured while the first and the second adhesive material are separated. The first curing agent is a silane coupling material, and the second curing agent is a metal chelate or a metal alcoholate; and a cation as a curing component is liberated, and the first and the second resin component cationically polymerize. Since the adhesive is cured at a lower temperature and in a shorter time period than conventional adhesives, an electrical device can be manufactured at a low temperature and in a short time period. Since the first adhesive material contains a silane coupling agent, the adhesive has a high adhesiveness with a first object to be adhered having a glass substrate. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供使用具有优异的保存性能的粘合剂的电气装置并且在低温下快速固化。解决方案：第一和第二粘合剂材料分别具有第一和第二固化剂。由于只有当第一和第二固化剂开始反应时，第一和第二树脂组分聚合，所以粘合剂在第一和第二粘合材料分离的同时不固化。第一固化剂是硅烷偶联材料，第二固化剂是金属螯合物或金属醇化物; 并且作为固化成分的阳离子被释放，第一和第二树脂成分阳离子聚合。由于粘合剂在比常规粘合剂更低的温度和更短的时间内固化，所以可以在低温和短时间内制造电气装置。由于第一粘合剂材料含有硅烷偶联剂，所以粘合剂与具有玻璃基板的第一待粘合物具有高粘合性。版权所有（C）2009，JPO＆INPIT

92. 发明专利

JPWO2006109407A1 フリップチップ実装方法及びバンプ形成方法有权
公开(公告)号：JPWO2006109407A1
公开(公告)日：2008-10-09
申请号：JP2007512427
申请日：2006-03-16
申请人：松下電器産業株式会社
发明人：孝史北江 , 孝史北江 , 中谷　誠一 , 誠一中谷 , 靖治辛島 , 靖治辛島 , 山下　嘉久 , 嘉久山下 , 貴志一柳 , 貴志一柳
IPC分类号： H01L21/60
CPC分类号： H01L24/16 , H01L21/4853 , H01L21/563 , H01L21/6835 , H01L24/11 , H01L24/13 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/11001 , H01L2224/11003 , H01L2224/1141 , H01L2224/11502 , H01L2224/11522 , H01L2224/13022 , H01L2224/13099 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/16225 , H01L2224/16227 , H01L2224/165 , H01L2224/2741 , H01L2224/27436 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29291 , H01L2224/29299 , H01L2224/29305 , H01L2224/29309 , H01L2224/29311 , H01L2224/29313 , H01L2224/29316 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/83192 , H01L2224/832 , H01L2224/83856 , H01L2224/83862 , H01L2224/83874 , H01L2224/8388 , H01L2224/83885 , H01L2224/83886 , H01L2224/83887 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/0102 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/12042 , H01L2924/14 , H01L2924/1579 , H01L2924/381 , H01L2924/3841 , H05K3/323 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H05K2203/0264 , H05K2203/087 , H05K2203/1178 , Y02P70/613 , H01L2924/01031 , H01L2924/01049 , H01L2924/01051 , H01L2924/01083 , H01L2924/00011 , H01L2924/00015 , H01L2924/066 , H01L2924/06 , H01L2924/0675 , H01L2924/0695 , H01L2924/00 , H01L2224/05599
摘要：第1の電子部品(2)上にハンダ粉(5a)と樹脂(4)を含むハンダ樹脂組成物(6)を載置し、第1の電子部品(2)の接続端子(3)と第2の電子部品(8)の電極端子(7)とが対向するように配置し、第1の電子部品(2)とハンダ樹脂組成物を加熱して第1の電子部品(2)に含まれるガス発生源(1)からガスを噴出させ、ガス(9a)をハンダ樹脂組成物(6)中で対流させることにより、ハンダ粉(5a)をハンダ樹脂組成物(6)中で流動させ、接続端子(3)及び電極端子(7)上に自己集合させて接続端子(3)と電極端子(7)とを電気的に接続させる。これにより、狭ピッチで配線された半導体チップの電極端子と回路基板の接続端子とを高い接続信頼性で接続できるフリップチップ実装方法と回路基板上に実装するためのバンプ形成方法を提供する。

93. 发明专利

JP2008211241A Method for processing base 有权
标题翻译：加工基地方法
公开(公告)号：JP2008211241A
公开(公告)日：2008-09-11
申请号：JP2008112130
申请日：2008-04-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MIZUKOSHI MASATAKA , IMAIZUMI NOBUHIRO , ISHIZUKI YOSHIKATSU
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/563 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/1147 , H01L2224/13099 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/83191 , H01L2224/83194 , H01L2224/838 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/13091 , H01L2924/1579 , H01L2924/19041 , H01L2924/00 , H01L2924/00015 , H01L2224/29099 , H01L2224/48 , H01L2924/013 , H01L2924/01049
摘要： PROBLEM TO BE SOLVED: To achieve a semiconductor device having high reliability, which can form metal terminals at low cost and which can be mounted at low damage, the metal terminals having uniform height and smoothness and allowing connection under low load. SOLUTION: Electrodes 5 and an insulating film 6 are both formed of materials having such a property that: they are solid and do not exhibit the adhesiveness at room temperature; they exhibit the adhesiveness at least at a first temperature higher than the room temperature; and they cure at least at a second temperature higher than the first temperature. Cutting work is performed by using a hard bite composed of diamond or the like so that the surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a may become flat continuously and then planarization is performed. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题为了实现具有高可靠性的半导体器件，其可以以低成本形成金属端子并且可以以低损伤安装，金属端子具有均匀的高度和平滑度并且允许在低负载下连接。电极5和绝缘膜6均由具有以下特性的材料形成：它们是固体并且在室温下不表现出粘合性; 它们至少在高于室温的第一温度下表现出粘合性; 并且它们至少在高于第一温度的第二温度下固化。通过使用由金刚石等构成的硬质咬合来进行切削加工，使得半导体芯片1a的电极5和绝缘膜6的表面可以连续变平，然后进行平坦化。版权所有（C）2008，JPO＆INPIT

94. 发明专利

JP4130668B2 Processing method of the base 有权
标题翻译：空值
公开(公告)号：JP4130668B2
公开(公告)日：2008-08-06
申请号：JP2005159364
申请日：2005-05-31
申请人：富士通株式会社
发明人：延弘今泉 , 正孝水越 , 義克石月
IPC分类号： H01L21/60 , G06K19/07 , G06K19/077 , G06K19/10
CPC分类号： H01L24/13 , H01L21/563 , H01L24/02 , H01L24/06 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05578 , H01L2224/06102 , H01L2224/1134 , H01L2224/1147 , H01L2224/1184 , H01L2224/13028 , H01L2224/13082 , H01L2224/13144 , H01L2224/1357 , H01L2224/13639 , H01L2224/13644 , H01L2224/13664 , H01L2224/13669 , H01L2224/16106 , H01L2224/16225 , H01L2224/2784 , H01L2224/32225 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/8113 , H01L2224/81132 , H01L2224/81191 , H01L2224/83121 , H01L2224/83191 , H01L2224/83856 , H01L2924/00 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/13091 , H01L2924/19041 , Y10T29/49126 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099
摘要： The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.
摘要翻译：本发明实现了一种高可靠性的半导体器件，其允许在低负载和低成本下形成具有均匀高度，平坦和平滑的金属端子并且以低损伤安装。电极5和绝缘膜6均由具有固体特性的材料形成，并且在室温下不显示粘合性，并且在不低于第一温度的温度下显示粘附性，并且在不低于第二温度高于第一温度。半导体芯片1a的电极5和绝缘膜6的表面与硬质切削工具一样平坦化，如金刚石等。

95. 发明专利

JP4129837B2 Method of producing the mounting structure 有权
公开(公告)号：JP4129837B2
公开(公告)日：2008-08-06
申请号：JP2003157805
申请日：2003-06-03
申请人：松下電器産業株式会社
发明人：寛十河 , 正浩小野
IPC分类号： H01L21/60 , H05K3/32 , H05K1/18 , H05K3/34
CPC分类号： H01L2224/1134 , H01L2224/73104
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a packaging structure of high reliability wherein a shortcircuit is not generated between connecting parts which are adjacent to each other even if a gap between terminal electrodes of a semiconductor device becomes narrow, and to provide a connector. SOLUTION: In the manufacturing method, through holes 11 are formed in a resin film 7 and a lifting sheet 10 on the terminal electrodes 8 of a circuit board 9, and the through holes 11 are filled with a conductive adhesive 13; the lifting sheet 10 is exfoliated; projection electrodes 3 of the semiconductor device 1 are aligned on the conductive adhesive 13; and packaging is performed. The pierced hole 11 is formed as an inverse tapered shape wherein the diameter of a circuit board 9 side is greater than that of a semiconductor device 1 side. As a result, spreading of the conductive adhesive 13 by pushing at the time of packaging is restrained. COPYRIGHT: (C)2005,JPO&NCIPI

96. 发明专利

JP2008177364A Method of manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2008177364A
公开(公告)日：2008-07-31
申请号：JP2007009462
申请日：2007-01-18
申请人： Denso Corp , 株式会社デンソー
发明人： TANAKA MASAAKI , SAITO TAKASHIGE
IPC分类号： H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/29019 , H01L2224/73104 , H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of raising connection reliability, while simplifying a manufacturing process, and to provide the semiconductor device. SOLUTION: Protrusions are respectively formed on electrode forming surfaces in the respective semiconductor chip forming regions of a wafer. An electrical insulating bonding member is arranged to cover the whole electrode forming surfaces of the semiconductor chip forming regions including the protrusions with respect to the wafer with the protrusions formed thereon. The wafer with the bonding member arranged thereon is cut into a plurality of semiconductor chips, and then, the bonding member is pressurized, thereby exposing the tip ends of the protrusions from the bonding member. The semiconductor chip with the bonding member arranged therein and the different semiconductor chip are positioned by defining the protrusions exposed from the bonding member as optical position reference, and then the electrodes of these two semiconductor chips are electrically connected via a bump in the positioning state. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种能够提高连接可靠性的半导体器件的制造方法，同时简化制造工艺，并提供半导体器件。解决方案：在晶片的各个半导体芯片形成区域中的电极形成表面上分别形成突起。电绝缘接合构件被布置成覆盖形成有突起的相对于晶片的包括突起的半导体芯片形成区域的整个电极形成表面。将其上布置有接合构件的晶片切割成多个半导体芯片，然后对粘合构件进行加压，从而使接合构件的突起的前端露出。通过将从接合构件露出的突起限定为光学位置参考，将其中布置有接合构件的半导体芯片和不同的半导体芯片定位，然后这两个半导体芯片的电极经由位于定位状态的凸块电连接。版权所有（C）2008，JPO＆INPIT

97. 发明专利

JP2007311637A Method of forming bump-like connecting member 审中-公开
标题翻译：形成类似连接会员的方法
公开(公告)号：JP2007311637A
公开(公告)日：2007-11-29
申请号：JP2006140469
申请日：2006-05-19
申请人： Canon Inc , キヤノン株式会社
发明人： TAKEMURA MASAO , HIROZAWA TOSHIAKI , WATABE IKUTOMO
IPC分类号： H01L21/60
CPC分类号： H01L24/742 , H01L2224/11 , H01L2224/1134 , H01L2224/1184 , H01L2224/73104 , H01L2224/73204 , H01L2224/742 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a method of forming bump-like connecting members by which a reliability and a heat dissipation property of an electrical connection can be improved in a plurality of bump-like connecting members, for performing the electrical connection or a thermal connection between two members by mutually bonding the two members. SOLUTION: In bump-like connecting members 105 for mutually, electrically or thermally connecting the two members, a region deforming in case of bonding the bump-like connecting members by leveling is formed so that a cross section in the perpendicular direction to the bonding direction may be decreased. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种形成凸起状连接构件的方法，通过该方法可以在多个凸起状连接构件中提高电连接的可靠性和散热性能，以进行电连接或两个构件之间的热连接。解决方案：在用于相互，电或热连接两个构件的凸起状连接构件105中，在通过调平接合凸起状连接构件的情况下变形的区域被形成为使得垂直于可以降低接合方向。版权所有（C）2008，JPO＆INPIT

98. 发明专利

JP2007214346A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007214346A
公开(公告)日：2007-08-23
申请号：JP2006032371
申请日：2006-02-09
申请人： Sumitomo Bakelite Co Ltd , 住友ベークライト株式会社
发明人： KATSURAYAMA SATORU
IPC分类号： H01L23/29 , H01L21/60 , H01L23/31
CPC分类号： H01L24/81 , H01L23/3171 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/1182 , H01L2224/11822 , H01L2224/11848 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13562 , H01L2224/13582 , H01L2224/1369 , H01L2224/1401 , H01L2224/1601 , H01L2224/16227 , H01L2224/273 , H01L2224/2731 , H01L2224/27312 , H01L2224/2732 , H01L2224/27416 , H01L2224/27436 , H01L2224/27848 , H01L2224/29016 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/73103 , H01L2224/73104 , H01L2224/73204 , H01L2224/81024 , H01L2224/81355 , H01L2224/81395 , H01L2224/831 , H01L2224/83192 , H01L2224/83193 , H01L2224/83855 , H01L2224/83856 , H01L2224/92 , H01L2224/92125 , H01L2224/94 , H01L2924/3512 , H01L2924/35121 , H01L2224/11 , H01L2924/014 , H01L2924/0665 , H01L2924/00012 , H01L2924/01082 , H01L2924/01047 , H01L2924/01029 , H01L2924/01051 , H01L2924/01083 , H01L2924/01049 , H01L2924/01024 , H01L2924/00014 , H01L2224/27 , H01L21/78
摘要： PROBLEM TO BE SOLVED: To provide a sealing structure for preventing the cracking or the peeling-off in the joint between a semiconductor chip and a solder electrode or in the joint between a circuit board and a solder electrode, etc. in the flip-chip bonding scheme using the solder electrode. SOLUTION: The semiconductor chip 1 is electrically connected to the pad 5 on the circuit board 6 via the solder electrode 3. The joint between the semiconductor chip 1 and the solder electrode 3 is fixed by a first fixture 2 consisting of a first resin material. The first fixture 2 consisting of the first resin material is provided laminarly on the surface of the semiconductor chip 1 on the side of the solder electrode 3. Further, the joint between the solder electrode 3 and the pad 5 on the circuit board 6 is fixed by a second fixture 4 consisting of a second resin material. The second fixture 4 consisting of the second resin material is manufactured of a resin material different from that of the first fixture 2 consisting of the first resin material. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于防止半导体芯片和焊料电极之间或电路板和焊料电极之间的接合处的接合处的破裂或剥离的密封结构等使用焊料电极的倒装芯片接合方案。解决方案：半导体芯片1通过焊料电极3电连接到电路板6上的焊盘5.半导体芯片1和焊料电极3之间的接合体由第一固定件2固定，第一夹具2由第一树脂材料。由第一树脂材料构成的第一夹具2以半导体芯片1的焊料电极3侧的表面层叠地设置。此外，焊料电极3与电路基板6上的焊盘5的接合是固定的通过由第二树脂材料组成的第二固定件4。由第二树脂材料构成的第二固定件4由与由第一树脂材料构成的第一固定件2不同的树脂材料制成。版权所有（C）2007，JPO＆INPIT

99. 发明专利

JP3927759B2 Mounting method of electronic components onto a circuit board 有权
公开(公告)号：JP3927759B2
公开(公告)日：2007-06-13
申请号：JP2000156287
申请日：2000-05-26
申请人：松下電器産業株式会社
发明人：一人西田
IPC分类号： H01L21/60 , H05K3/32 , H01L21/56 , H01L23/485 , H05K3/22
CPC分类号： H01L24/11 , H01L21/563 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/05624 , H01L2224/11334 , H01L2224/1134 , H01L2224/11822 , H01L2224/13144 , H01L2224/1357 , H01L2224/1379 , H01L2224/138 , H01L2224/16225 , H01L2224/27436 , H01L2224/29076 , H01L2224/29078 , H01L2224/29101 , H01L2224/2919 , H01L2224/29399 , H01L2224/32225 , H01L2224/45144 , H01L2224/48624 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/75251 , H01L2224/75252 , H01L2224/7598 , H01L2224/81048 , H01L2224/81191 , H01L2224/81395 , H01L2224/81801 , H01L2224/83101 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/83851 , H01L2224/83855 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/01052 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/3011 , H01L2924/3511 , H05K3/321 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： When mounting an IC chip 1 on a circuit board 4, bumps 3 are formed on electrodes 2 on the IC chip, and the bumps and the electrodes of the circuit board are aligned in position with each other with interposition of an insulative thermosetting resin 6 having no conductive particle between the electrodes of the circuit board and the bumps. The IC chip is pressed against the circuit board with a pressure force of not smaller than 20 gf per bump by a heated head 8 so as to perform warp correction of the IC chip and the board, while the resin interposed between the IC chip and the circuit board is hardened to bond the IC chip and the circuit board together.

100. 发明专利

JP2007005688A Method for packaging semiconductor device 审中-公开
标题翻译：包装半导体器件的方法
公开(公告)号：JP2007005688A
公开(公告)日：2007-01-11
申请号：JP2005186476
申请日：2005-06-27
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： KATO HIROKI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16 , H01L2224/274 , H01L2224/73104 , H01L2224/75 , H01L2224/75745 , H01L2224/83191 , H01L2924/01079
摘要： PROBLEM TO BE SOLVED: To provide a method for packaging a semiconductor device by which high-density packaging can be realized on a substrate by a simple method.
SOLUTION: According to the method for packaging the semiconductor device, the semiconductor device 11 having several connectors 12 is electrically connected on the substrate having conductive parts through an adhesive material in the form of film and is flip chip mounted on it. In this case, an adhesive material 33 which is larger than the outermost periphery A of the several connectors 12 of the semiconductor device 11 is sandwiched between the several connectors 12 of the semiconductor device 11 and the conductive parts of the substrate and the semiconductor device 11 is mounted by heating and pressing by a bonding tool.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种用于通过简单的方法在基板上实现高密度封装的半导体器件的封装方法。解决方案：根据用于封装半导体器件的方法，具有多个连接器12的半导体器件11通过膜形式的粘合剂材料电连接到具有导电部件的基板上，并且安装在其上。在这种情况下，比半导体装置11的多个连接器12的最外周面A大的粘合剂材料33被夹在半导体装置11的多个连接器12和基板的导电部分和半导体装置11之间通过粘合工具的加热和加压来安装。版权所有（C）2007，JPO＆INPIT

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