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91. 发明专利

JPH04246078A ELEVATOR 失效
公开(公告)号：JPH04246078A
公开(公告)日：1992-09-02
申请号：JP923591
申请日：1991-01-29
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO
IPC分类号： B66B5/12 , B66B7/06
摘要： PURPOSE:To prevent the operation of an elevator from being stopped due to the vertical movement of a compensation sheave 1 by temperature change or the elongation of a main wire 11. CONSTITUTION:Threre are provided a potentiometer 2 which detects the vertical movement of a compensation sheave 1, and a motor 3 which compensates the positions of limit switches 7A, 7B by the output of the detector 2 following the movement amount of the compensation sheave 1.

92. 发明专利

JPH0472667A CONDUCTIVITY MODULATION MOSFET 失效
公开(公告)号：JPH0472667A
公开(公告)日：1992-03-06
申请号：JP25790190
申请日：1990-09-26
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , WATANABE KIMINORI , NAKAGAWA AKIO
IPC分类号： H01L29/78 , H01L29/739
摘要： PURPOSE:To make a switching characteristic good at a turn-off operation by a method wherein the injection efficiency of a p-type drain layer is lowered when the carrier density in an n-type layer becomes larger than the impurity concentration in the p-type drain layer. CONSTITUTION:A turn-off operation is executed by applying a negative bias or a zero bias to a gate electrode 6. Thereby, the inversion layer in a channel region 7 under the gate electrode 6 disappears, and electrons are not injected from a source layer 3. In this state, electrons which have been accumulated inside an element are discharged to an n type diffusion layer 9 inside a drain layer 8 until their injection becomes low. Holes are passed through a p-type base layer 2 and reach the n type source layer 3. That is to say, the same operation as that of an anode short structure is executed substantially, and a switching speed becomes fast at the turn-off operation.

93. 发明专利

JPH03171774A HIGH WITHSTAND VOLTAGE PLANAR ELEMENT 失效
公开(公告)号：JPH03171774A
公开(公告)日：1991-07-25
申请号：JP31137189
申请日：1989-11-30
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI , YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/861
摘要： PURPOSE:To realize good contact state between an electrode and a high resistance film, to eliminate local field concentration and to improve withstand voltage of an element by connecting each of both ends of the high resistance film to the electrode through an ohmic contact layer. CONSTITUTION:Polycrystalline silicones 9, 10 of low resistance are arranged at both ends of a high resistance film 7 for its foundation as an ohmic contact layer to extend from the both sides of the film 7. An anode electrode 11 and a cathode electrode 12 are directly connected to both ends of the high resistance film 7; and at the same time, also connected to low resistance polycrystalline silicon films 9, 10. According to this constitution, ohmic contact state is remarkably improved between the anode electrode 11 and the high resistance film 7, and the cathode electrode 12 and the high resistance film 7. Therefore, a depletion layer extends uniformly inside an element, thereby making field concentration hardly occure and realizing high withstand voltage.

94. 发明专利

JPH02198175A CONDUCTIVITY-MODULATION TYPE MOSFET 失效
公开(公告)号：JPH02198175A
公开(公告)日：1990-08-06
申请号：JP1830989
申请日：1989-01-27
申请人： TOSHIBA CORP
发明人： WATANABE KIMINORI , YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO
IPC分类号： H01L29/68 , H01L29/739 , H01L29/78
摘要： PURPOSE:To increase a latchup current and to reduce a cost by providing a second conductivity type low impurity concentration diffused layer diffused on the surface of a wafer of a range from a drain isolating layer to a source layer. CONSTITUTION:A second conductivity type low impurity concentration diffused layer 15 diffused on the surface of a wafer from a drain isolating layer 5 of the second conductive type to a source layer 4 is provided. Since the impurity diffused layer has a concentration gradient in a depthwise direction different from an epitaxial layer, if a total impurity amount is constant, the concentration can be enhanced in the vicinity of the surface as compared with that of the epitaxial layer. Accordingly, when the surface concentration is the same as that of a prior art, the inner impurity concentration of a first conductivity type base layer 3 can be enhanced. Thus, a latchup current can be raised without increasing a threshold value. Since an epitaxial wafer is not employed, its manufacturing cost is reduced.

95. 发明专利

JPH02161752A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02161752A
公开(公告)日：1990-06-21
申请号：JP31709588
申请日：1988-12-15
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , FURUKAWA KAZUYOSHI , WATANABE KIMINORI , YASUHARA NORIO
IPC分类号： H01L21/762 , H01L21/76
摘要： PURPOSE:To enable a resist film to be applied without forming steps in subsequent formation of a groove and to avoid disconnection when a plurality of grooves having different depths are formed by etching in a semiconductor substrate, by providing a pattern for both first and second etchings prior to performing the etchings. CONSTITUTION:An Si substrate 11 is heated to a high temperature within oxygen to produce a thin SiO2 film 12 for preventing cracks. The film 12 is then removed such that it is left only on the top face of the substrate. An oxidation- resistant Si3N4 film 13 is deposited on the film 12 and an photo-etching is performed so that the laminate consisting of the films 13 and 12 is left unetched in a predetermined size only on a second etching region. Then, an SiO2 film 14 is deposited on the exposed surface of the substrate 11 so as to surround the laminate and is provided with a window corresponding to a first etching region, A deep groove 15 is then formed in the window by etching and the film 14 around it is substituted with a new film 16. The laminate film 12, 13 is then removed and the second etching is performed on the exposed surface part of the substrate 11 to provide a shallow groove 17 there.

96. 发明专利

JPH02134014A OVERCURRENT PROTECTION CIRCUIT FOR CONDUCTION MODULATION TYPE MOSFET 失效
公开(公告)号：JPH02134014A
公开(公告)日：1990-05-23
申请号：JP28669488
申请日：1988-11-15
申请人： TOSHIBA CORP
发明人： KOBAYASHI EIICHI , YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO , WATANABE KIMINORI , DOMON TOMOKAZU
IPC分类号： H02H7/20 , H03K17/08 , H03K17/687
摘要： PURPOSE:To decrease the dielectric strength of a DGBI FET (Double Gate Bipolar mode FET) or the like even when the DGBI FET or the like is employed for a device using a high power voltage by protecting the DGBI FET or the like from an overcurrent. CONSTITUTION:If a load circuit 3 is short-circuited, an auxiliary gate G2 of a DGBI FET 2 is biased forward at first to attain the unipolar mode to the FET 2, a source level is given to a main gate G1 after a prescribed time from that point of time to turn off the DGBI FET 2. Thus, while a secondary breakdown of the DGBI FET 2 is prevented, it is turned off. Since the DGBI FET 2 or the like is protected from an overcurrent in this way, even when the DGBI FET 2 or the like is used for a device employing a high power supply voltage, the dielectric strength rating of the DGBI FET 2 or the like is decreased.

97. 发明专利

JPS6373564A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6373564A
公开(公告)日：1988-04-04
申请号：JP21750986
申请日：1986-09-16
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO , WATANABE KIMINORI
IPC分类号： H01L29/68 , H01L29/06 , H01L29/40 , H01L29/78
摘要： PURPOSE:To improve reliability by disposing a resistive field plate film so as to simultaneously cover a second main electrode and a control electrode. CONSTITUTION:An oxide film 24 is formed onto the surface of an n type drain layer 12 shaped onto an n type drain layer 11 through epitaxial growth, the oxide film 24 is etched to a predetermined pattern, and a gate electrode 16 is formed through a gate oxide film 15. p-type base layers 13 are formed, using the gate electrode 16 and the oxide film 24 as masks. An oxide film is shaped into a diffusion window by the gate electrode 16, and an n type layer 25 as well as n type sources 14 are formed, employing the oxide film and the gate electrode 16 as masks. The surface of the gate electrode 16 is coated with an oxide film 17, a hole is bored to a contact section in the gate electrode 16, and a source electrode 18 and a metallic gate electrode 19 are shaped. An a-Si film is deposited on the whole surface of an element, and a resistive field plate film 27 is formed. A drain electrode 20 is shaped onto the surface of a wafer. Accordingly, the element having high reliability can be acquired through a simple process.

98. 发明专利

JPS61261920A OVERCURRENT PROTECTING CIRCUIT FOR CONDUCTIVE MODULATION TYPE MOSFET 失效
公开(公告)号：JPS61261920A
公开(公告)日：1986-11-20
申请号：JP10331185
申请日：1985-05-15
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO , OKATSUCHI CHIHIRO
IPC分类号： H03K17/08 , H02H3/087 , H02H7/20
摘要： PURPOSE:To improve the reliability by constituting an overcurrent protecting circuit of a conductive modulation type (FET), of a drain-source voltage detecting circuit of the FET, and a circuit for dropping a gate-source voltage of the FET by an output of said circuit. CONSTITUTION:When a short circuit accident is generated in a load 3, and an overcurrent flows to a conductive modulation type MOSFET 1, and a voltage generated in a resistance 13 of a voltage detecting circuit exceeds a Zener voltage of a Zener diode 16, a thyristor SCR 14 is turned on. In this case, a MOSFET 15 is inserted in advance in series to the thyristor 14, therefore, a delay time of a delaying circuit consisting of a floating capacity of this gate and a resistance 19 is made longer than a turn-on time of the FET 1. As a result, a high gate voltage can be applied to the FET except flowing of an overcurrent to the FET 1, and a turn-on failure is prevented. Also, when the SCR 14 becomes on, a gate-source voltage of the FET 1 becomes the sum of the SCR 14 and the MOSFET 15, and becomes below the minimum gate voltage easily.

99. 发明专利

JPS61261919A OVERCURRENT PROTECTING CIRCUIT FOR CONDUCTIVE MODULATION TYPE MOSFET 失效
公开(公告)号：JPS61261919A
公开(公告)日：1986-11-20
申请号：JP10330885
申请日：1985-05-15
申请人： TOSHIBA CORP
发明人： YAMAGUCHI YOSHIHIRO , NAKAGAWA AKIO , OKATSUCHI CHIHIRO
IPC分类号： H03K17/08 , H02H3/087 , H02H7/20 , H03K17/0812 , H03K17/082 , H03K17/567 , H03K17/687
摘要： PURPOSE:To raise the reliability by constituting an overcurrent protecting circuit of a conductive modulation type MOSFET (BIFET), of a drain-source voltage detecting circuit, and a circuit for dropping a gate-source voltage of the BIFET by an output of said circuit. CONSTITUTION:When an accident is generated in a load 3, and an overcurrent flows to a conductive modulation type MOSFET 1, a voltage corresponding to an on-voltage of the FET 1 is obtained in a resistance 13 of a voltage detecting circuit. This voltage is applied to a gate of a MOSFET 14 through a diode 17, and when this gate voltage exceeds a threshold value, a gate-source voltage of the FET 1 drops to the sum of an on-voltage of the FET 14 and a forward voltage of a diode 15 and cuts off the overcurrent of the FET 1. In this case, a charge which has been accumulated in a gate input capacity of the FET 14 and a discharge time constant by a resistance 16 are made large, and a discharge time of the MOSFET 14 is made longer than a vibration period of a source-drain voltage of the FET 1. As a result, it is prevented that the FET 1 is turned on again.

100. 发明专利

JPS59167061A Thyristor with function of protecting over-voltage 失效
标题翻译：具有保护过电压功能的THYRISTOR
公开(公告)号：JPS59167061A
公开(公告)日：1984-09-20
申请号：JP4074483
申请日：1983-03-14
申请人： Toshiba Corp
发明人： OOHASHI HIROMICHI , YOSHIDA JIROU , YAMAGUCHI YOSHIHIRO , AKAGI JIYUNKO
IPC分类号： H01L29/74 , H01L29/861
CPC分类号： H01L29/7424
摘要： PURPOSE:To obtain a large strength of di/dt by increasing the value of non destructive breakdown current at junction bending part by a method wherein the P type second base layers divided into two are provided on the N type first base layer, and, when the P-N junction is exposed to the surface on cathode electrode side while bending devided ends, the surface of the first base layer positioned between the divided ends is covered with a P type layer. CONSTITUTION:The N type first base layer 12 is laminated on a P type emitter layer 11 provided with an anode electrode 15 on the back surface, the P-N junction J2 is generted by providing the P type second base layers 13 divided into two on said base layer, and the function bending parts 100 are provided at the divided ends. In this construction, the surface layer part of the layer 12 positioned between the bending parts 100 ie kept covered with the P type region 30, and a pluraity of N type emitter regions 14 are diffusion-formed in these thyristor regions divided into two, respectively, which emitters are then isolated by means of a shallow P type layer 140 connected to the region 30. Thereafter, cathode electrodes 16 are adhered on the regions 14.
摘要翻译：目的：通过在N型第一基底层上设置分为两部分的P型第二基底层的方法，通过增加接合弯曲部分的非破坏性击穿电流的值来获得较大的di / dt强度， PN结暴露于阴极电极侧的表面，同时弯曲的端部，位于分开的端部之间的第一基底层的表面被P +型层覆盖。构成：N型第一基底层12层叠在背面设置有阳极电极15的P型发射极层11上，PN结J2通过在所述基底上设置分为两部分的P型第二基底层13 层，功能弯曲部100设置在分割端。在这种结构中，位于被保持覆盖有P +型区域30的弯曲部分100之间的层12的表面层部分和N型发射极区域14的一部分在这些可控硅区域中被扩散形成，两个，然后通过连接到区域30的浅P +型层140隔离这些发射体。之后，阴极电极16粘附在区域14上。

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