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91. 发明专利

JPS63200555A SEMICONDUCTOR PACKAGE STRUCTURE 失效
公开(公告)号：JPS63200555A
公开(公告)日：1988-08-18
申请号：JP3368787
申请日：1987-02-17
申请人： HITACHI LTD
发明人： INOUE KOICHI , KURIHARA YASUTOSHI , YATSUNO KOMEI , SAWAHATA MAMORU , TAKAHASHI MASAAKI
IPC分类号： H01L23/52 , H01L23/34
摘要： PURPOSE:To form a soft buffer layer between the 1st dielectric substrate and the 2nd dielectric substrate of a semiconductor package and improve the reliability of the coupling of the two substrates whose thermal expansion coefficients are different from each other by a method wherein the 1st dielectric substrate is made of aluminum nitride and the 2nd dielectric substrate is made of ceramics and the two substrates are coupled together with soft metal which is active to ceramics as adhesive. CONSTITUTION:A silicon chip 1 is fixed to an IC support member 31 by a die-bonding layer 2. An interconnection member 7 is composed of a multilayer board containing conducting paths 11. The support member 31 is housed in the recess formed in the rear of the member 7 and the chip is positioned at the center of a stepped hole. The support member 31 is made of aluminum nitride AlN and used as a 1st dielectric substrate and the interconnection member 7 is made of ceramics and used as a 2nd dielectric member. The support member 31 and the member 7 are coupled together with an adhesion member 6. The adhesion member 6 is made of relatively soft metal which is active to ceramics. Wire bonding electrodes 13 and 15 are formed on the surfaces of the member 7 and the chip 1 respectively.

92. 发明专利

JPS62108786A METALLIZED ALUMINUM NITRIDE BODY AND MANUFACTURE 失效
公开(公告)号：JPS62108786A
公开(公告)日：1987-05-20
申请号：JP24707385
申请日：1985-11-06
申请人： HITACHI LTD
发明人： KURIHARA YASUTOSHI , TAKAHASHI MASAAKI , INOUE KOICHI , SAWAHATA MAMORU , YATSUNO KOMEI
IPC分类号： H01L23/12 , C04B41/88 , H05K3/12

93. 发明专利

JPS6293960A PACKAGE STRUCTURE EMPLOYING SILICON CARBIDE 失效
公开(公告)号：JPS6293960A
公开(公告)日：1987-04-30
申请号：JP23326685
申请日：1985-10-21
申请人： HITACHI LTD
发明人： INOUE KOICHI , KURIHARA YASUTOSHI , YATSUNO KOMEI , SAWAHATA MAMORU , TAKAHASHI MASAAKI , YAMAMOTO TAKANOBU
IPC分类号： H01L23/14 , H01L23/08 , H01L23/15
摘要： PURPOSE:To obtain package structure with low thermal resistance and high reliability by a method wherein the 1st dielectric which is made of material containing at least SiC and has a predetermined thermal expansion coefficient and on which a semiconductor substrate is fixed is mechanically coupled with the 2nd dielectric. CONSTITUTION:A wiring member 7 in which conductive paths 11 are formed, an SiC member 301 which is metallized with Mo, a W member 302, adhesive metal 303 and an adhering member 6 (Al coated with Al alloy containing Si on both sides) are combined and pressed and heated in vacuum to bond the wiring member 7 and the members 301 and 302. Then a die-bonding part and wire bonding electrodes 13 are formed by nonelectrolytic plating of gold. The gold film on the backside of a chip 1 is heated and converted into a gold-Si eutectic solder film and the Si chip 1 is bonded. gold wires 14 are connected between the wire bonding electrodes on the front side of the chip 1. A sealing member 9 is bonded to the member 7 by an adhering member 8, which is Au-Sn eutectic solder, to complete a package.

94. 发明专利

JPS6216548A SEMICONDUCTOR PACKAGE STRUCTURE 失效
公开(公告)号：JPS6216548A
公开(公告)日：1987-01-24
申请号：JP15555785
申请日：1985-07-15
申请人： HITACHI LTD
发明人： INOUE KOICHI , KURIHARA YASUTOSHI , YATSUNO KOMEI , SAWAHATA MAMORU , TAKAHASHI MASAAKI
IPC分类号： H01L23/15 , H01L23/08 , H01L23/12
摘要： PURPOSE:To obtain a highly reliable semiconductor package structure as well as to enable to easily build its water-cooled structure by a method wherein the first dielectric substrate with the semiconductor base is integrally formed with the second dielectric substrate, and also the material thereof shall be a sintered body of an Al nitride (AlN) film. CONSTITUTION:A dielectric substrate 12 for support and wiring comprising conductive paths 11, gold-metallized electrodes for an Si chip 1, and wire-bonding electrodes (substrate side) 13, is prepared. Then the gold film adhered on the back surface of the Si chip 1 is heated down into a gold-Si eutectic solder used as a die-bonding member 2 to bond the Si chip 1 at the prescribed position on the dielectric substrate 12 for support and wiring. The wire-bonding electrodes (chip side) 15 as many as the wire-bonding electrodes (substrate side) 13 are already formed on the surface side of the Si chip 1 and the mutually corresponding wire-bonding electrodes are connected to one another using fine gold wires 14. Lastly a cap member 9 is boned on the dielectric substrate 12 for support and wiring using cap bonding members 8.

95. 发明专利

JPS6161533B2 失效
公开(公告)号：JPS6161533B2
公开(公告)日：1986-12-26
申请号：JP581780
申请日：1980-01-23
申请人： HITACHI LTD
发明人： TAKAHASHI MASAAKI , MISAWA YUTAKA , YATSUNO KOMEI
IPC分类号： H01L21/316 , H01L23/29 , H01L23/31

96. 发明专利

JPS6156870B2 失效
公开(公告)号：JPS6156870B2
公开(公告)日：1986-12-04
申请号：JP10428680
申请日：1980-07-31
申请人： HITACHI LTD
发明人： YOKOYAMA TAKASHI , IKEDA TAKAE , MISAWA YUTAKA , TAKAHASHI MASAAKI
IPC分类号： H01L23/29 , H01L21/312 , H01L23/31

97. 发明专利

JPS60163438A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60163438A
公开(公告)日：1985-08-26
申请号：JP1830084
申请日：1984-02-06
申请人： HITACHI LTD
发明人： MISAWA YUTAKA , TAKAHASHI MASAAKI , YATSUNO KOUMEI , MINAGAWA TADASHI
IPC分类号： H01L25/07 , H01L21/306 , H01L21/308 , H01L21/329
摘要： PURPOSE:To reduce the quantity of slush production at the time of disposal of waste liquid by a method wherein a substance whose ratio of mixture of hydrofluoric acid, nitric acid, phosphoric acid, and water has been set at a vol% in a specific range is used as the etchant for the titled device of Si having an Mo electrode. CONSTITUTION:The range of composition of an etchant which can well keep the characteristic of inhibition of a semiconductor device such as a high-tension diode treated by etching with a solution made of hydrofluoric acid (HF), nitric acid (HNO3), and water and thereafter molded with glass is in a range shown by hatching, a range satisfying the conditios: 1) the rate of water composition is 20.5% (straight line L1) or more and 40% (straight lines L1, L2) or less at volume ratio; 2) the rate of composition of hydrofluoric acid is 1% (straight line L3) or more at volume ratio; further, 3) the rate of composition of nitric acid is larger than that of hydrofluoric acid (a straight line L4 compbines points for the equal rate of composition of both).

98. 发明专利

JPS59171125A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59171125A
公开(公告)日：1984-09-27
申请号：JP4501483
申请日：1983-03-17
申请人： Hitachi Ltd
发明人： MISAWA YUTAKA , TAKAHASHI MASAAKI
IPC分类号： H01L21/301 , H01L21/306
CPC分类号： H01L21/306
摘要： PURPOSE:To perform a uniform etching without detriment to electrical characteristics by a method wherein a plurality of square-shaped semiconductor pellets formed on the wafer having the face (111) as the main face are cut, and when the above cut face is processed using an alkali etchant, the cut face is set at 45 deg. against the lattice direction of the wafer. CONSTITUTION:A PNN type wafer 11 is formed using an Si substrate having the face (111), and an Ni electrode 12 and a solder layer 13 are laminated on both front and back sides of said wafer 11. Then, the wafer 11 is formed into an individual pellet 16 by cutting it along the cutting line 15 which is set at 45 deg. against the orientation flat 14 of the face (100) or (110), which is in the direction of 45 deg. against lattice direction and a lead 17 is attached to the layer 13. Subsequently, the above is soaked into a hot caustic soda aqueous solution, an etching is performed on the cut face of the pellet 16, under coating resin 18 is applied thereon, and molding resin 19 is coated on the whole surface.
摘要翻译：目的：通过切割形成有以面（111）为主面的晶片上形成的多个方形半导体颗粒的方法进行均匀蚀刻而不损害电特性，并且当上述切割面使用碱蚀刻剂，切割面设定在45度。抵抗晶片的晶格方向。构成：使用具有面（111）的Si衬底形成PNN +型晶片11，并且在所述晶片11的正面和背面层叠Ni电极12和焊料层13.然后，晶片 11通过沿设置在45度的切割线15切割成单个颗粒16而形成。相对于面向（100）或（110）的定向平面14，该面朝向45度的方向。在层13上附着引线17，接着，将上述内容物浸入热的苛性钠水溶液中，在颗粒16的切割面上进行蚀刻，涂布树脂18被涂敷并且在整个表面上涂覆模制树脂19。

99. 发明专利

JPS59132134A Method and apparatus for etching semiconductor device 失效
标题翻译：用于蚀刻半导体器件的方法和装置
公开(公告)号：JPS59132134A
公开(公告)日：1984-07-30
申请号：JP532883
申请日：1983-01-18
申请人： Hitachi Ltd
发明人： MISAWA YUTAKA , TAKAHASHI MASAAKI , YATSUNO KOUMEI , HIDAKA TOSHIYUKI , FUJIEDA SADAO , MONMA NOBUO , TAKAHASHI MASAO
IPC分类号： H01L21/306
CPC分类号： H01L21/306
摘要： PURPOSE:To prevent a plating of a metal on lead wires by keeping the lead wires connected to each region of a semiconductor device at the same potential and etching the lead wires by an alkaline solution to which the metal is added. CONSTITUTION:A semiconductor device in which lead wires 10, 11 are bonded with both main surfaces of a diode pellet 13, the inside thereof has a P-N junction, through solder layers 12 is etched. The lead wire 11 is inserted into a hole bored to the support plate 20A of a jig 20, and the lead wire 10 is fixed by a hold-down member 20B. The jig 20, the support plate 20A and the hold- down member 20B are formed by a corrosion-resisting and conductive material, and short-circuit both lead wires 10, 11 to keep them at the same potential. The jig 20 is dipped in an etching liquid 30, which contains tin 40 adjusting potential between the diode pellet 13 and the etching liquid and consists of NaOH and water, to remove the fouling of the pellet and a strain layer.
摘要翻译：目的：通过将连接到半导体器件的每个区域的引线保持在相同的电位来防止引线上的金属电镀，并通过添加金属的碱性溶液蚀刻引线。构成：其中引线10,11与二极管芯片13的两个主表面接合的半导体器件，其内部具有通过焊料层12的P-N结。引线11插入到夹具20的支撑板20A上钻孔，并且引线10由压紧构件20B固定。夹具20，支撑板20A和压紧构件20B由耐腐蚀和导电材料形成，并且使两个引线10,11短路以使它们保持相同的电位。将夹具20浸入蚀刻液30中，该蚀刻液30含有调节二极管芯片13与蚀刻液之间的电位的锡40，由NaOH和水构成，以除去颗粒和应变层的污垢。

100. 发明专利

JPS564239A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS564239A
公开(公告)日：1981-01-17
申请号：JP7974179
申请日：1979-06-26
申请人： HITACHI LTD
发明人： TAKAHASHI MASAAKI , MISAWA YUTAKA , YATSUNO KOUMEI
IPC分类号： H01L51/05 , H01L21/316 , H01L21/331 , H01L29/73 , H01L51/40
摘要： PURPOSE:To perform sealing-up with a crystalline glass whose main constituents are ZnO, B2O5 and SiO2, by changing a medium comprising diethylene glycol dibutyl ether and isobutyl methacrylate ester into ash or splashing the medium at a temperature not higher than the softening point of the crystalline glass. CONSTITUTION:2-50wt% of isobutyl methacrylate is dissolved in diethylene glycol dibutyl ether. The solution is kneaded with a crystalline glass whose main constituents are ZnO, B2O3 and SiO2 to prepare printing ink. The molecular weight of the isobutyl methacrylate is set at 10 or less so that changing to ash and splashing are facilitated, the quantity of residual carbon is reduced and the electric properties of a semiconductor device are not deteriorated. The viscosity of the ink is adjusted to about 1.5-5X10 cp. The ink is printed on a P-N junction. The printed ink is maintained at the softening point of the glass for about 5-30min. As a result, no bubbles and pinholes are produced, glass projections are greatly decreased, following work is facilitated, pattern accuracy is enhanced and production yield is improved.

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