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91. 发明专利

JPS5692642A CONSTANT DESIGNATING SYSTEM 失效
公开(公告)号：JPS5692642A
公开(公告)日：1981-07-27
申请号：JP17247779
申请日：1979-12-26
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI
IPC分类号： G06F9/34 , G06F9/30
摘要： PURPOSE:To enable to produce constants at the register designation section, by providing the means which detects whether the register belonging to M sets of registers provided with the register designation section is designated or not and also providing the constant number generating circuit. CONSTITUTION:In a computer providing M(=8) sets of general registers 1, when the instruction in which the location of 8-th and 12nd bit of the instruction register 8 is zero, is executed, the content of the register 1 designated at the register designation section R1 is set to the 1st operand data register 2, and that designated with the designation section R2 opens the gate G1 with the detecion signal of the constant number designation and detection circuit 6 and is set to the 2nd operand data register 3. The data of the registers 2 and 3 is operated at an operator 4 and the result is set to the register 5. When the head bit of the designation section R2 is 1, the gate G2 is opened with the detection signal of the circuit 6, the constant corresponding to the content of the section R2 is picked up from a constant generating circuit 7 and set to the register 3.

92. 发明专利

JPS5687293A SHIFT REGISTER 失效
公开(公告)号：JPS5687293A
公开(公告)日：1981-07-15
申请号：JP16253079
申请日：1979-12-14
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI
IPC分类号： G11C19/00
摘要： PURPOSE:To reduce the quantity of hardware, by performing both the writing and reading at a time with no mutual overlap with use of a register file which can write and read several data at a time. CONSTITUTION:The register file 1 consists of the n-stage register, and the data given from the writing address buses 2 and 3 are written into the register stages of the addresses shown by the writing counters 6 and 7 and at the same time read onto the reading address buses 4 and 5 form the address stages shown by the reading address counters 10 and 11. The counter 6 counts repetitively 0-(n). The count difference among counters is indicated so that an overlap is avoided between the count difference (a) of the counters 6 and 10 and the count difference (c) of the counters 7 an 11. As a result, both shift registers of (a+1) stages and (c+1) stages work at a time for the file 1.

93. 发明专利

JPS5684029A INSPECTION SYSTEM FOR CLOCK CIRCUIT 失效
公开(公告)号：JPS5684029A
公开(公告)日：1981-07-09
申请号：JP16105579
申请日：1979-12-12
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI
IPC分类号： H03K5/19 , H03K5/15
摘要： PURPOSE:To detect a fault of a clock distribution by providing counters at two optional points in a clock separating circuit having the greater arrival time difference of a clock, sent from a common clock oscillator, than clock cycles. CONSTITUTION:As the power source is put to work, the output of either one of clock oscillators 1 and 2 which is predetermined is distributed to respective parts via preceding clock distributing circuit 3. The clock passed through phase adjusting circuits 4 and 5 and fan-out group 6 is supplied to counter 9 via signal line 14. The clock passed through phase adjusting circuit 4 and fan-out group 7 is supplied to counter 8 via signal line 18. Values of counters 8 and 9 are inputted to count difference detecting circuit 10, which outputs the difference in value between both the counters. The difference between both the counters is compared with a value set in register 12 in advance and when their dissidence is detected, comparing circuit 11 generates error display output 16.

94. 发明专利

JPS5668862A DATA PROCESSING DEVICE 失效
公开(公告)号：JPS5668862A
公开(公告)日：1981-06-09
申请号：JP14525179
申请日：1979-11-09
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI , UCHIDA KEIICHIROU , TANAKURA YOSHIYUKI
IPC分类号： G06F7/02 , G06F9/305 , G06F15/78 , G06F17/16
摘要： PURPOSE:To facilitate generation of programs, by selecting a vector register to make operation possible without exchange of elements by casuing a mask register to function for operation between elements of the vector register. CONSTITUTION:Vector register 1 of M-number elements is provided, and elements of registers designated as operands are taken out successsively, and operation between elements is executed by operating circuit 7. M-number mask registers 2 are provided correspondingly to respective elements of register 1, and data read from register 1 is held in register 5 according to designation of elements of registers 2. Contents of address counter 3 are counted up by +1 and are set to register 9 and are used as the index. Data which should be compared with contents of register 5 is held in register 6, and contents of registers 5 and 6 are compared with each other by circuit 7, and on a basis of the comparison operating condition, contents of register 5 are stored in register 6, and register 1 is selected to execute operation.

95. 发明专利

JPS562521A TEMPERATURE ALARM DETECTING SYSTEM 失效
公开(公告)号：JPS562521A
公开(公告)日：1981-01-12
申请号：JP7872679
申请日：1979-06-22
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI , TAKEMURA ATSUO
IPC分类号： G01K3/08 , G08B21/00
摘要： PURPOSE:To make it possible to detect an alarm by detecting and comparing a difference in temperature between two points to a fixed value. CONSTITUTION:At the air inlet and outlet of unit 1, temperature detection parts T and T' are provided. With signals sent from temperature detection parts T and T', control part C' detects inlet air temperature Tai and outlet air temperature Tao to find a difference in temperature between the both, and further compares it to the sum of preset temperature rise DELTAT due to the normal heating of unit 1 and detected temperature DELTATd of abnormal temperature increment in unit 1. Once (Tao-Tai)>=(DELTAT+DELTATd) is detected, an alarm signal is sent out to unit 1 via signal line l2.

96. 发明专利

JPS55164318A TEMPERATURE ALARM DETECTING SYSTEM 失效
公开(公告)号：JPS55164318A
公开(公告)日：1980-12-22
申请号：JP7190279
申请日：1979-06-08
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI , TAKEMURA ATSUO
IPC分类号： G01K7/24 , G01K7/00
摘要： PURPOSE:To make high-precision temperature alarm detection possible even for change of environmental conditions of the unit, by providing plural temperature detecting parts different in detection temperature and by selecting one temperature detecting part most suitable for the environment of the unit. CONSTITUTION:Temperature alarm detecting part 1' is provided with plural temperature detecting parts T1-Tn different in detection temperature, and one of temperature detecting parts T1-T3 which is suitable for the environment is selected according to environmental conditions by select switch S which sets connection to control part C. Control part C is operated on a basis of the result of one selected temperature detecting part Ti, so that high-precision temperature alarm detection is possible.

97. 发明专利

JPS5176029A Kiokuseigyohoshiki 失效
公开(公告)号：JPS5176029A
公开(公告)日：1976-07-01
申请号：JP122975
申请日：1974-12-26
申请人： Fujitsu Ltd
发明人： SHIMOMURA KEISUKE , OOKAWA MASAYUKI , TAMURA HIROSHI , HIROWATARI SHOICHI
IPC分类号： G06F12/08 , G06F13/00

98. 发明专利

JPS5112734A 失效
公开(公告)号：JPS5112734A
公开(公告)日：1976-01-31
申请号：JP8388674
申请日：1974-07-22
申请人： FUJITSU LTD
发明人： SHIMOMURA KEISUKE , OOKAWA MASAYUKI , TAMURA HIROSHI , HIROWATARI SHOICHI
IPC分类号： G06F12/12 , G06F13/00

99. 发明专利

JPS6346872B2 失效
公开(公告)号：JPS6346872B2
公开(公告)日：1988-09-19
申请号：JP14691682
申请日：1982-08-26
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI , ITO KENICHI , OKAMOTO TETSUO
IPC分类号： G06F9/30 , G06F9/48 , G06F15/78 , G06F17/16

100. 发明专利

JPS63180171A INFORMATION PROCESSOR 失效
公开(公告)号：JPS63180171A
公开(公告)日：1988-07-25
申请号：JP1203387
申请日：1987-01-21
申请人： FUJITSU LTD
发明人： ITO MIKIO , TAMURA HIROSHI , UCHIDA KEIICHIRO
IPC分类号： G06F12/00 , G06F12/08 , G06F12/10 , G06F15/78 , G06F17/16
摘要： PURPOSE:To improve the performance of a system by accessing both a main memory and an extended memory so that no exception of address conversion is generated for a unit having no instruction execution invalidating function. CONSTITUTION:For an access request given from a scalar unit 4, access control is given only to a main memory 1 at all times via a selection circuit 8 of a memory access controller 3. While the access control is given to both the memory 1 and an extended memory 2 via a switch circuit 9 of the device 3 for the access request given from a vector unit 5. In other words, a virtual address caused by an access request of the unit 5 is converted into a real address within the unit 5. then the circuit 9 decides whether the corresponding area is included in the memory 1 or 2. Thus the device 3 is controlled so that access is given to the memory 1 or 2. In such constitution, the unit 5 generates no exception of address conversion even though the unit 5 has no instruction execution invalidating function. Thus the information can be processes at a high speed.

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