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91. 发明专利

JP5019890B2 A method of manufacturing a semiconductor device 有权
公开(公告)号：JP5019890B2
公开(公告)日：2012-09-05
申请号：JP2007007665
申请日：2007-01-17
申请人：エスケーハイニックス株式会社SK hynix Inc.
发明人：鉉修金 , 鍾萬金
IPC分类号： H01L21/8242 , H01L21/762 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/308 , H01L27/10855 , H01L27/10888

92. 发明专利

JP5017570B2 Pattern formation method of a semiconductor element 有权
公开(公告)号：JP5017570B2
公开(公告)日：2012-09-05
申请号：JP2007236691
申请日：2007-09-12
申请人：エスケーハイニックス株式会社SK hynix Inc.
发明人： ▲ちょる▼圭卜 , 槿道潘
IPC分类号： H01L21/027 , G03F7/11 , G03F7/20 , G03F7/40 , H01L21/3065
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3143 , H01L21/3146 , H01L21/3185
摘要： A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer, selectively etching the second hard mask layer and the first hard mask layer by using a line/space mask as an etching mask to form a second hard mask layer pattern and a first hard mask layer pattern, forming an insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer and its underlying first hard mask layer pattern by using the insulating film as an etching mask to form a fourth hard mask layer pattern overlying a third hard mask layer pattern, removing the insulating film and the fourth hard mask layer pattern, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask, to form a fine pattern.

93. 发明专利

JP2012155830A Semiconductor memory chip and multi-chip package using the same 有权
标题翻译：半导体存储芯片和使用该芯片的多芯片封装
公开(公告)号：JP2012155830A
公开(公告)日：2012-08-16
申请号：JP2011196381
申请日：2011-09-08
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： KO BOK RIM , KIN KOJUN
IPC分类号： G11C11/401 , H01L27/10
CPC分类号： G11C7/1045 , G11C7/1012 , G11C7/1084 , G11C2207/105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory chip which facilitates packaging of a multi-chip package and allows a constant loading of signals transmitted by bonding for connection between the semiconductor memory chip and a pad of the multi-chip package.SOLUTION: A semiconductor memory chip comprises: a first pad part where a first data signal, a first strobe signal, and a first mask signal are input; and a first selective transmission part for transmitting, in a first mode, the first data signal, the first strobe signal, and the first mask signal to a first write path circuit, and transmitting, in a replacement mode, the first data signal, the first strobe signal, and the first mask signal to a second write path circuit.
摘要翻译：要解决的问题：提供一种便于封装多芯片封装的半导体存储器芯片，并且允许通过结合传输的信号的恒定负载以用于半导体存储器芯片和多芯片封装的焊盘之间的连接。解决方案：半导体存储器芯片包括：第一焊盘部分，其中输入第一数据信号，第一选通信号和第一屏蔽信号; 以及第一选择性传输部件，用于在第一模式中将第一数据信号，第一选通信号和第一屏蔽信号发送到第一写入路径电路，并且以替换模式发送第一数据信号，第一选通信号，并将第一屏蔽信号送到第二写路径电路。版权所有（C）2012，JPO＆INPIT

94. 发明专利

JP2012155828A Refresh circuit 有权
标题翻译：刷新电路
公开(公告)号：JP2012155828A
公开(公告)日：2012-08-16
申请号：JP2011163587
申请日：2011-07-26
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： PARK SANG IL
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/40618 , G11C11/408
摘要： PROBLEM TO BE SOLVED: To provide a refresh circuit capable of reducing electric current consumed during a refresh operation by preventing a row address maintaining a prescribed level from being unnecessarily latched.SOLUTION: A refresh circuit comprises: an enable pulse generation part for generating a first enable pulse including a pulse periodically generated during a refresh period and a second enable pulse including a pulse generated at the time point of completion of counting for all bits of a first row address; a first address latch for latching the first row address to generate a first latch address synchronously with the first enable pulse; and a second address latch for latching a second row address to generate a second latch address and a third latch address synchronously with the second enable pulse.
摘要翻译：要解决的问题：提供一种刷新电路，其能够通过防止维持规定级别的行地址被不必要地锁定来减少刷新操作期间消耗的电流。解决方案：刷新电路包括：使能脉冲产生部分，用于产生包括在刷新周期期间周期性产生的脉冲的第一使能脉冲和包括在所有位的计数完成时产生的脉冲的第二使能脉冲的第一行地址; 第一地址锁存器，用于锁存第一行地址以与第一使能脉冲同步地产生第一锁存器地址; 以及第二地址锁存器，用于锁存第二行地址以与第二使能脉冲同步地产生第二锁存器地址和第三锁存器地址。版权所有（C）2012，JPO＆INPIT

95. 发明专利

JP4997371B2 Mask pattern forming method 有权
公开(公告)号：JP4997371B2
公开(公告)日：2012-08-08
申请号：JP2007313394
申请日：2007-12-04
申请人：エスケーハイニックス株式会社SK hynix Inc.
发明人：貴 ▲ワン▼ 沈 , 宇榮鄭
IPC分类号： G03F7/40 , G03F7/038 , G03F7/039 , H01L21/027

96. 发明专利

JP4997316B2 Semiconductor memory device 有权
公开(公告)号：JP4997316B2
公开(公告)日：2012-08-08
申请号：JP2010104087
申请日：2010-04-28
申请人：エスケーハイニックス株式会社SK hynix Inc.
发明人：國善崔
IPC分类号： G11C11/409 , G11C11/4097 , G11C7/06 , G11C7/10 , G11C7/18 , G11C8/10 , G11C11/408 , G11C11/4091
CPC分类号： G11C11/4087 , G11C7/062 , G11C7/1051 , G11C7/18 , G11C8/10 , G11C11/4091 , G11C11/4097

97. 发明专利

JP4992018B2 Manufacturing method of a transistor of the semiconductor memory device 有权
公开(公告)号：JP4992018B2
公开(公告)日：2012-08-08
申请号：JP2005178793
申请日：2005-06-20
申请人：エスケーハイニックス株式会社SK hynix Inc.
发明人：在根 ▲オ▼ , 世億張 , 龍洙金
IPC分类号： H01L21/8242 , H01L21/336 , H01L27/108 , H01L29/78
CPC分类号： H01L29/7851 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L27/10879 , H01L29/66621 , H01L29/66795
摘要： Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.

98. 发明专利

JP2012142587A Method of forming dielectric film, and method of forming capacitor of semiconductor element using the same 审中-公开
标题翻译：形成介质膜的方法和使用其形成半导体元件的电容器的方法
公开(公告)号：JP2012142587A
公开(公告)日：2012-07-26
申请号：JP2012035989
申请日：2012-02-22
申请人： Sk Hynix Inc , エスケーハイニックス株式会社SK hynix Inc.
发明人： KIL DEOK SIN , HONG KWON , YEOM SEUNG JIN
IPC分类号： H01L27/108 , C23C16/40 , C23C16/56 , H01L21/31 , H01L21/316 , H01L21/336 , H01L21/8242 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： C23C16/40 , C23C16/45529 , C23C16/45531 , H01L21/02178 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L21/3141 , H01L21/31616 , H01L21/31641 , H01L27/10814 , H01L28/40
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a dielectric film of a semiconductor element, as well as a method of forming a capacitor, capable of improving dielectric characteristic and leakage current characteristic.SOLUTION: The present invention relates to a method for forming a dielectric film comprising a zirconium oxide (ZrO) and aluminum oxide (AlO) on a wafer by atomic layer deposition method. A source gas in which one Zr atom and one Al atom constitute one molecule is injected in a chamber, to form [ZrO]x[AlO]y film comprising ZrOand AlO(here, x and y are positive numbers) on the wafer, and the step is repeated to form a dielectric film having thickness of 30-500 Å, comprising ZrOand AlO.
摘要翻译：解决的问题：提供形成半导体元件的电介质膜的方法以及能够改善介电特性和漏电流特性的形成电容器的方法。解决方案：本发明涉及形成包含氧化锆（ZrO·SB POS =“POST”> 2 ）和氧化铝（Al O 3 ）。将一个Zr原子和一个Al原子构成一个分子的源气体注入到室中，以形成[ZrO x [Al 包含ZrO 2 和Al 2 的薄膜，在晶片上的SB> O 3 （这里，x和y是正数），并且重复该步骤以形成厚度为30-500的电介质膜，包括ZrO 2 和 3 。版权所有（C）2012，JPO＆INPIT

99. 发明专利

JP4987458B2 Data output circuit and method of the semiconductor memory device 有权
公开(公告)号：JP4987458B2
公开(公告)日：2012-07-25
申请号：JP2006347551
申请日：2006-12-25
申请人：エスケーハイニックス株式会社SK hynix Inc.
发明人：炯東李
IPC分类号： G11C11/4093 , H03K19/0175
CPC分类号： H03K19/094
摘要： A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable signal. A main driver generates last output data to a common node from the pull-up and down signals. An assistant pre-driver generates an assistant drive signal, which is activated when the rising data disagrees with the falling data, in correspondence with inputs of the rising data, the falling data, the rising clock, the falling clock, and a pipe output control signal. An assistant main driver generates assistant last output data to the common node from the pull-up and down signals in accordance with a state of the assistant drive signal.

100. 发明专利

JP4981396B2 Temperature information output device and how to perform that of semiconductor memory device 有权
公开(公告)号：JP4981396B2
公开(公告)日：2012-07-18
申请号：JP2006269942
申请日：2006-09-29
申请人：エスケーハイニックス株式会社SK hynix Inc.
发明人：椿錫鄭
IPC分类号： G01K7/01 , G01K15/00 , G11C11/406 , H01L21/8242 , H01L27/108
CPC分类号： G11C29/02 , G11C5/147 , G11C29/021 , G11C29/028 , G11C2029/5002

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