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1. 发明专利

JPS60226169A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60226169A
公开(公告)日：1985-11-11
申请号：JP8335084
申请日：1984-04-25
申请人： TOSHIBA KK
发明人： NIITSU YOUICHIROU , NIHEI HIROYUKI , KANZAKI KOUICHI
IPC分类号： H01L21/76 , H01L21/8238 , H01L27/092
摘要： PURPOSE:To obtain a semiconductor device, incorporating CMOS transistors, capable of enhanced integration and of withstanding higher punch-through voltages by a method wherein N and P wells are formed aligned to each other so that the region between them where they cancel each other may be reduced in size. CONSTITUTION:A polycrystalline Si layer 16' is retained on the side walls of an Si3N4 pattern 14' and SiO2 pattern 15' built in the previous stage of manufacture. The retained polycrystalline Si layer 16' and SiO2 pattern 15' act as masks in a process of driving P ions into a substrate 11. Further, with the retained polycrystalline Si layer 16', SiO2 pattern 15', etc. removed, a thermal treatment is performed wherein a thick oxide film 18 and N well 20 are formed with the Si3N4 pattern 14' acting as a mask. Then, the Si3N4 pattern 14', first polycrystalline layer 13 and first SiO2 film 12 are removed. Finally, the thick oxide film 18 acts as a mask in a process of introducing B ions into the substrate 11 for the formation of a P well 21. In such a design, the region where the N well 20 and P well 21 offset each other may be as narrow as 1mum as measured from the well edges. Accordingly, enhanced integration is realized incorporating finer-structure elements.

2. 发明专利

JPS6094774A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6094774A
公开(公告)日：1985-05-27
申请号：JP20225283
申请日：1983-10-28
申请人： TOSHIBA KK
发明人： SHINADA KAZUYOSHI , MAKITA KOUJI , KANZAKI KOUICHI
IPC分类号： H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To improve the withstand property by heat treating at the temperature higher than the oxidizing temperature before the oxidizing step after the step of adding an impurity into a polycrystalline silicon layer. CONSTITUTION:A field oxide film 2 is buried in a P type silicon substrate 1 to form a thermally oxidized film 3. Then, a polysilicon layer 4 is accumulated, and with POCl3 as a diffusion source it is diffused at 1,000 deg.C. Then, an oxidation is performed at 950 deg.C to form a thin polysilicon oxide film 5. Then, a polysilicon film 6 is accumulated, and with POCl3 as a diffusion source it is diffused at 900 deg.C. With a resist film 7 as a mask a polysilicon layer 6 and a polysilicon oxide film 5, the layer 4 and the film 3 are sequentially etched, removed, and arsenic ions are implanted. Then, the film 7 is removed, oxidized at 950 deg.C to simultaneously form an oxidized film 8, an N type drain region 9 and a source region 10. Subsequently, a CVD oxide film 11 is accumulated, the films 11, 8 are then opened, and a drain electrode 12 and a source electrode 13 are provided.

3. 发明专利

JPS60176270A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60176270A
公开(公告)日：1985-09-10
申请号：JP3206184
申请日：1984-02-22
申请人： TOSHIBA KK
发明人： KOBAYASHI HIROSHI , NIHEI HIROYUKI , KANZAKI KOUICHI
IPC分类号： H01L21/336 , H01L29/78
摘要： PURPOSE:To reduce junction capacitance, and to increase the speed of operation by forming a P type pocket layer to a substrate under the side wall of a gate electrode so as to be able to be completely distinguished from N type ion implantation layers in source and drain regions. CONSTITUTION:A gate insulating film 32 and a P type ion implantation layer 33 are formed on an Si substrate 31 in succession, a polycrystalline Si layer to which P is doped is shaped, and a gate electrode 34 is formed through patterning. When an Si oxide film 35 and an Al film 36 are deposited in succession, grooves 37a, 37b can be formed to the side wall of the gate electrode 34. Opening sections 38a, 38b are shaped through etching, and P type ion implantation layers 39a, 39b are formed to the substrate 31 in a self-control manner. The residual Al film 36 is removed, and the ions of an N type impurity are implanted to the substrate 31 to shape shallow N type ion implantation layers 40a, 40b. Spacers 41a, 41b are formed on the side wall of the gate electrode 34, N type ion implantation layers 42a, 42b are shaped, and P type pocket layers 43a, 43b, a source region 44 and a drain region 45 are each formed through activation.

4. 发明专利

JPS60176272A MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS60176272A
公开(公告)日：1985-09-10
申请号：JP3282884
申请日：1984-02-23
申请人： TOSHIBA KK
发明人： MIKATA YUUICHI , SHINADA KAZUYOSHI , MORI SEIICHI , KANZAKI KOUICHI , USAMI TOSHIROU
IPC分类号： H01L29/78 , H01L21/8247 , H01L29/788 , H01L29/792
摘要： PURPOSE:To increase the withstanding voltage of a second gate oxide film, and to improve memory maintaining characteristics by forming a second insulating film on the surface of a first nonsingle crystal silicon film, depositing and patterning a second nonsingle crystal silicon film and shaping a source and a drain. CONSTITUTION:A field oxide film 22, a first thermal oxide film 23, a first polycrystalline Si film 24, a second thermal oxide film 25 to which phosphorus is doped and a second polycrystalline Si film 26 are formed on a P type Si substrate in succession. A first gate oxide film 28, a floating gate 29, a second gate oxide film 30 and a control gate 31 are shaped through patterning while using a photo-resist pattern 27 as a mask. As ions are implanted. The photo-resist pattern 27 is removed, and an oxide film 32 and N type source and drain regions 33, 34 are shaped through thermal oxidation. A PSG film 35 is deposited, contact holes 36, 36 are bored through etching, an Al-Si film is deposited, and a source electrode 37 and a drain electrode 38 are shaped through patterning.

5. 发明专利

JPS6089980A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6089980A
公开(公告)日：1985-05-20
申请号：JP19707583
申请日：1983-10-21
申请人： TOSHIBA KK
发明人： KANZAKI KOUICHI
IPC分类号： H01L29/88 , H01L21/8247 , H01L29/788 , H01L29/792 , H01L29/861 , H01L29/94
摘要： PURPOSE:To enable to apply to a nonvolatile memory by providing the current and voltage characteristic between a substrate or a semiconductor layer and a conductive layer asymmetrically, thereby forming a capacity having rectifying property. CONSTITUTION:A semiconductor substrate 11 which has a flat main surface 10 on the surface is prepared. An insulating film 13 which is formed of an SiO2 film or the like becoming irregular surface 12 on the surface is laminated on the surface 10 of the substrate 11. The thickness of the film 13 is suitably set to a range of 100-10,000Angstrom . Then, a conductive layer 14 which is formed of polycrystalline Si is formed on the surface 12 to obtain a semiconductor device which becomes a capacitor 15. The current and voltage characteristic of the capacitor 15 has remarkable difference between the case that a positive voltage is applied and the case that a negative voltage is applied as shown in the curve III, exhibiting rectifying characteristic.

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