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1. 发明专利

JP2005286079A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005286079A
公开(公告)日：2005-10-13
申请号：JP2004097371
申请日：2004-03-30
申请人： Nippon Telegr & Teleph Corp , Shindengen Electric Mfg Co Ltd , 新電元工業株式会社 , 日本電信電話株式会社
发明人： SHIMIZU TAKASHI , SHIMOKAWA FUSAO , MAKIHARA MITSUHIRO , SATO MAKOTO , YODOGAWA HIROYUKI , YAMAZAKI TAKESHI
IPC分类号： H01L21/329 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing current leaks, decreasing the number of erroneous operations, and reducing power consumption.
SOLUTION: A voltage source 11a applies a potential higher than that of an n
+ diffusion layer 41c to the p
+ diffusion layer 43c of the cell to be driven. This causes a current to flow to a thin-film resistor 30c for the production of heat. A voltage source 11b applies a potential higher than the potential of the p
+ diffusion layer 43 to the n
+ diffusion layers 41 of the cells other than the cell to be driven. A voltage source 12 applies a negative potential to a p-substrate 50. No current leak occurs because the bias between the n
+ diffusion layers 41 of the cells other than the cell to be driven, and the p
+ diffusion layer 43 is reverse to the bias between the n
- diffusion 42 and the p-substrate 50.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够防止电流泄漏，减少错误操作次数并降低功耗的半导体器件。解决方案：电压源11a将电位高于n + 扩散层41c的电位施加到待驱动电池的p + / SP>扩散层43c。这导致电流流向薄膜电阻器30c以产生热量。电压源11b将高于p + 扩散层43的电位的电位施加到除被驱动的单元之外的单元的n + SP + +扩散层41。电压源12向p基板50施加负电位。由于除被驱动的单元之外的单元的n - 扩散层42和p-衬底50之间的偏置相反。版权所有：（C）2006，JPO＆NCIPI

2. 发明专利

JP2005227357A Heating circuit 审中-公开
标题翻译：加热电路
公开(公告)号：JP2005227357A
公开(公告)日：2005-08-25
申请号：JP2004033629
申请日：2004-02-10
申请人： Nippon Telegr & Teleph Corp , Shindengen Electric Mfg Co Ltd , 新電元工業株式会社 , 日本電信電話株式会社
发明人： SHIMIZU TAKASHI , SHIMOKAWA FUSAO , MAKIHARA MITSUHIRO , SATO MAKOTO , YODOGAWA HIROYUKI , YAMAZAKI TAKESHI
IPC分类号： G02B26/08
摘要： PROBLEM TO BE SOLVED: To provide a heating circuit capable of assuring the areas of transistors in which the electric power required for driving thin-film heaters is supplied without changing the area of one cell. SOLUTION: Logic sections 1 have AND gates and storage elements. A selection signal line bus 2 includes a row signal line and a column signal line for applying signals to the logic sections 1. Gate signal line buses 3 connect the logic sections 1 and MOS arrays 4. The MOS arrays 4 have the thin-film heaters and field effect transistors which are arranged in a plurality in a matrix. The logic sections 1 are arranged around the MOS arrays 4. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够确保提供驱动薄膜加热器所需的电力的晶体管的面积而不改变一个单元的面积的加热电路。解决方案：逻辑部分1具有与门和存储元件。选择信号线总线2包括用于向逻辑部分1施加信号的行信号线和列信号线。栅极信号线总线3连接逻辑部分1和MOS阵列4.MOS阵列4具有薄膜加热器以及排列成矩阵状的多个场效应晶体管。逻辑部分1围绕MOS阵列4排列。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005228803A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005228803A
公开(公告)日：2005-08-25
申请号：JP2004033630
申请日：2004-02-10
申请人： Nippon Telegr & Teleph Corp , Shindengen Electric Mfg Co Ltd , 新電元工業株式会社 , 日本電信電話株式会社
发明人： SHIMIZU TAKASHI , SHIMOKAWA FUSAO , MAKIHARA MITSUHIRO , SATO MAKOTO , YODOGAWA HIROYUKI , YAMAZAKI TAKESHI
IPC分类号： H01L21/3065
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can suppress the reduction of pattern size of a polyimide film by etching and hardly changes device characteristics through processing; and to provide its manufacturing method.
SOLUTION: A polyimide is deposited on a semiconductor substrate 2 by spin coating so as to form a polyimide film 1. Next, an SiO
2 is deposited on the polyimide film 1 through CVD to form an SiO
2 film 3. The SiO
2 film 3 is subjected to patterning, and while the SiO
2 film 3 is used as a mask, the polyimide film 1 is dry-etched by a plasma 4 using O
2 . A thin SiO
2 film is deposited on the semiconductor substrate 2 including the polyimide film 1 through CVD, and a conductive film 5 as a material for a heater is deposited thereon by vacuum vapor deposition method or sputtering method. When the conductive film 5 is patterned by dry etching, an optional structure can be obtained.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供能够通过蚀刻抑制聚酰亚胺膜的图案尺寸的降低的半导体装置，并且通过加工几乎不改变装置特性; 并提供其制造方法。解决方案：通过旋涂将聚酰亚胺沉积在半导体衬底2上以形成聚酰亚胺膜1.接下来，通过CVD在聚酰亚胺膜1上沉积SiO 2 ，以形成 SiO 2 膜3.将SiO 2 膜3进行图案化，而当使用SiO 2 SB 3膜作为掩模时，聚酰亚胺薄膜1用等离子体4使用O SB SB2进行干式蚀刻。通过CVD将包括薄膜1的薄SiO 2薄膜沉积在包含聚酰亚胺薄膜1的半导体衬底2上，通过真空气相沉积法或溅射法沉积作为加热器材料的导电膜5。当通过干蚀刻图案化导电膜5时，可以获得任选的结构。版权所有（C）2005，JPO＆NCIPI

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