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1. 发明专利

JPS5322330A ADDRESS CONVERSION SYSTEM 失效
公开(公告)号：JPS5322330A
公开(公告)日：1978-03-01
申请号：JP9607076
申请日：1976-08-13
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD
发明人： TSUKIOKA KENICHI , TAJIMA SEIJIROU , KATOU MASAO , OOKAWA MASAYUKI
IPC分类号： G06F12/10 , G06F9/34 , G06F12/02
摘要： PURPOSE:To use the segment table commonly when an address is converted to an actual address.

2. 发明专利

JPS603025A MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS603025A
公开(公告)日：1985-01-09
申请号：JP10896683
申请日：1983-06-17
申请人： NIPPON ELECTRIC CO
发明人： TSUKIOKA KENICHI
IPC分类号： G06F9/22 , G06F9/26
摘要： PURPOSE:To reduce the bit-directional capacity of a control memory and improve ecomony by providing plural readout registers of the control memory, using them properly through a control means, and using the starting address of the control memory selectively. CONSTITUTION:The 1st control memory 2 is stored with mircoinstructions to be executed by a data processor, and those microinstructions are read out to a microinstruction register 3 and executed. The 2nd control memory 11 is stored with a specific field indicating the starting address of the routine of the microinstructions stored in the 1st control memory 11. For the purpose, readout registers 12 and 16 for the 2nd control memory 11 are provided and used properly to input the starting address of the 2nd control memory 11 to an address circuit 13 selectively.

5. 发明专利

JPS56137447A INFORMATION PROCESSOR 失效
公开(公告)号：JPS56137447A
公开(公告)日：1981-10-27
申请号：JP3948080
申请日：1980-03-27
申请人： NIPPON ELECTRIC CO
发明人： TSUKIOKA KENICHI
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
摘要： PURPOSE:To enable to give an interpretation of instruction code and access to control memory in high speed, by giving the advanced-fetch instruction to the instruction word buffer and bypassing the instruction word buffer so that the instruction code of the instruction word branched can be stored in the instruction code register. CONSTITUTION:The instruction word arranging circuit 2 which positions the instruction code of the instruction word read out from the instruction word buffer 1 to be executed next to the upper most byte with the instruction word counter 7 and instruction word length detecting circuit 8, is provided. The write-in data to the buffer 1 and the instruction code output from the circuit 2 are selected at the instruction code selection circuit 3 with the branch detection circuit 9 of the instruction word during execution at present. Further, the output of the circuit 3 is set and the instruction code register 4 storing it is provided. Thus the branched advance fetch instruction is written in the buffer 1 and the instruction code only is bypassed to the instruction buffer through the circuit 3 to speed up the access to the control memory of the branched instruction word at branch.

7. 发明专利

JPS5786924A TIMER DEVICE 失效
公开(公告)号：JPS5786924A
公开(公告)日：1982-05-31
申请号：JP16380280
申请日：1980-11-20
申请人： NIPPON ELECTRIC CO
发明人： TSUKIOKA KENICHI
IPC分类号： G06F1/14 , G06F9/48 , H03K17/28
摘要： PURPOSE:To eliminate the deterioration of timer precision and to eliminate the requirement to pay attention to the point in time of the occurrence of timer interruption, by adding a preset register circuit, a comparing circuit and a roll- over shift register circuit to a timer. CONSTITUTION:An output value 210 from a preset register 200 is compared by a comparing circuit 300 with an output value 120 from an interval timer 100 and when the both are coincident with each other, a signal 310 which carries the least significant digit bit of a roll-over shift register 500 by one bit is generated. Consequently, an interruption signal 610 continues until a clear signal 410 is applied, and a timer interruption signal 710 is outputted in response to a timer permission signal 620. Consequently, an accurate timer value is obtained without processing timer interruption through software with top priority, so an overhead accompanying timer processing is reduced.

8. 发明专利

JPS56137446A INFORMATION PROCESSOR 失效
公开(公告)号：JPS56137446A
公开(公告)日：1981-10-27
申请号：JP3947980
申请日：1980-03-27
申请人： NIPPON ELECTRIC CO
发明人： TSUKIOKA KENICHI
IPC分类号： G06F9/38
摘要： PURPOSE:To speed up the interpretation of instruction code and the access to the control memory at branch operation, by giving the instruction word fetched in advance to the instruction word buffer and providing the branched instruction code register every half length of the word. CONSTITUTION:The instruction word buffer 1 fetches and stores the continuous instruction words of a plurality. On the other hand, the branched instruction code register A41 and the branched code register B42 are provided every a half word. Thus, the interpretation of instruction code and access to the control memory at branch operation can be made in high speed.

10. 发明专利

JPS60168249A ADDRESS CONVERSION SYSTEM OF INPUT/OUTPUT DEVICE 失效
公开(公告)号：JPS60168249A
公开(公告)日：1985-08-31
申请号：JP2394684
申请日：1984-02-10
申请人： NIPPON ELECTRIC CO
发明人： TSUKIOKA KENICHI
IPC分类号： G06F13/12 , G06F12/10
摘要： PURPOSE:To designate addresses of a large-capacity main memory by providing a page table pointer as page table address words besides peripheral device control words. CONSTITUTION:A page table PT and page table address words PTAW arranged in the order of channel number are prepared in the main memory device. A page table base of the page table address word PTAW and a page number PN of an effective address which are obtained on a basis of the page table address word PTAW which is obtained in accordance with a channel number of a given peripheral device control word are combined to take out a page table word PTW from the page table PT. The taken-out page table word PTW and an intrapage address L of the effective address are combined to obtain an effective memory address of the main memory device.

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