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1. 发明专利

JPS561769A CONSTANT CURRENT CIRCUIT 失效
公开(公告)号：JPS561769A
公开(公告)日：1981-01-09
申请号：JP7721279
申请日：1979-06-19
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： MURATA MASANORI , ITOU MITSUTOSHI , AKAZAWA YUKIO , SUDOU TSUNETAKA
IPC分类号： H02M3/155 , G05F1/56 , G05F3/26 , H03K17/60
摘要： PURPOSE:To obtain the constant output current with the switching action by connecting two NPN transistors and one PNP transistor in a specified relationship. CONSTITUTION:Two NPN transistors and one PNP transistor are connected as illustrated. With the input terminal grounded, the NPN transistors Q1 and Q2 are turned off and no collector current flows in the transistor Q2. On the other hand, when the input terminal 1 is opened, the collector current of the PNP transistor Q3 mostly flows to the grounded terminal through the transistor Q1. At this point, current flows to the collector terminal at the level almost equal to multiplication of the collector current of the transistor Q1 by the emitter area ratio of the transistors Q1 and Q2. The collector current I3 of the transistor Q3 is as given by I3 (Vcc- VBE3)/R while the collector current I2 is as given by I2=A2(Vcc-VBE3)/A1.R (where, Vcc represents the external power source, VVE3 the voltage between the base and emitter terminals of the transistor Q3, R resistance and A1 and A2 the emitter area of the transistor Q1 and Q2). Accordingly, the resistance R can set the collector current I2 with the voltage Vcc being constant.

2. 发明专利

JPS561625A BINARY COUNTER 失效
公开(公告)号：JPS561625A
公开(公告)日：1981-01-09
申请号：JP7721179
申请日：1979-06-19
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： MURATA MASANORI , ITOU MITSUTOSHI , AKAZAWA YUKIO , SUDOU TSUNETAKA
IPC分类号： H03K23/58 , H03K23/00
摘要： PURPOSE:To increase the working velocity by inserting the 2nd and the 3rd inverters between the output terminal of the 1st FF connected to the input terminal of the 1st inverter and the wired AND to which the output terminals of the 2nd and subsequent FFs are connected. CONSTITUTION:Inverters 6 and 7 are inserted between output terminal 5 of FF1 connected to the input terminal of inverter 4 and wired AND wiring 3 to which the output terminals of the 2nd and subsequent FFs are connected. Now the input pulse is applied through terminal 1 with repetition of ON and OFF given to each FF, and thus the counter carries out the input pulses. Then the input terminal of inverter 6 becomes low in potential when the counting proceeds with the high potential secured for the input of inverter 7, and the output terminal holds the low potential when the output terminal of FF1 becomes low in potential. And the charge is given only to the parasitic capacity accompanied to the output terminal of inverter 6 when the output terminal of FF1 features the high potential. In this way, the working velocity can be increased easily for the counter.

3. 发明专利

JPS55124330A FLIPPFLOP CAPABLE OF COUNTING AND INITIAL SETTING 失效
公开(公告)号：JPS55124330A
公开(公告)日：1980-09-25
申请号：JP3193379
申请日：1979-03-19
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： AKAZAWA YUKIO , SUDOU TSUNETAKA , MURATA MASANORI , ITOU MITSUTOSHI
IPC分类号： H03K21/38 , H03K3/037 , H03K23/00
摘要： PURPOSE:To simplify the circuit constitution as well as realize both the miniaturization and the low power consumption, by forming the additional circuit of the initial value setting function with the FF circuit and the logic gate which is capable of the high-speed action for the initial value setting. CONSTITUTION:Initial setting input terminal 15 and counting-initial setting switch terminal 11 are connected to the input ends of the 1st and the 2nd NAND gates 31 and 32. And the output of gates 31 and 32 are supplied to the 3rd NAND gate 33. Furthermore, the output of gate 31 is supplied to the 4th NAND gate 34, and the output of gates 32 and 34 are supplied to NAND gate 35. The output of gate 33 is applied to reset terminal R of FF circuit 18; the output of gate 35 is applied to set terminal S of circuit 18; and the clock pulse sent from clock terminal 21 is applied to trigger terminal T. Then the number of the gates is reduced for the range during which signal R applied to terminal 11 reaches reset terminal R, and thus the speed of the initial value setting action is increased. And the counting speed is decided according to the velocity performance of circuit 18. In this way, the circuit constitution can be simplified.

4. 发明专利

JPS5621416A DIGITALLANALOGUE CONVERTING CIRCUIT 失效
公开(公告)号：JPS5621416A
公开(公告)日：1981-02-27
申请号：JP9781579
申请日：1979-07-31
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： MURATA MASANORI , ITOU MITSUTOSHI , SUDOU TSUNETAKA , AKAZAWA YUKIO
IPC分类号： H03M1/74 , H03K13/05
摘要： PURPOSE:To constitute a D/A converter by the integrated circuit of I L structure. CONSTITUTION:When only input terminal 1 is opened and other input terminals 11 and 21 are grounded, the current of contant current source 2 is flowed into transistor TR3, and currents equal to the current of constant current source 2 are flowed to TR4, 41, 42 and 43 which share base and emitter terminals with TR3. These currents become currents of TR5, 15, 25 and 35 respectively, and further, currents corresponding to emitter areas are flowed out from collectors to TR6, 16, 26 and 36 due to the current Miller effect. The current flowed from output terminal 7 becomes the sum of these currnts. Then, an output current of the quantity corresponding to the open input terminal can be obtained by combinations of opening and grounding of input terminals 1, 11 and 12.

5. 发明专利

JPS5374822A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS5374822A
公开(公告)日：1978-07-03
申请号：JP15034476
申请日：1976-12-16
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： YOSHIRI MAKOTO , KAWASHIMA ISAO , MUKAI HISAKAZU , YAMAMORI KAZUHIKO , MURATA MASANORI
IPC分类号： H03F3/68 , H03F3/04 , H04B3/36
摘要： PURPOSE:To reduce greatly change of the power current by securing constant identity between the sum of the current which flows to two transistors and the current of a constant current circuit.

6. 发明专利

JPS56115039A BINARY COUNTER 失效
公开(公告)号：JPS56115039A
公开(公告)日：1981-09-10
申请号：JP1733380
申请日：1980-02-15
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： AKAZAWA YUKIO , KAWARADA KUNIYASU , HISHINUMA ESAO , MURATA MASANORI , IDE TETSUO , IWAMOTO HIROSHI
IPC分类号： H03K23/58 , H03K23/00
摘要： PURPOSE:To realize not only a high speed but a low power consumption with a simple constitution of circuit, by adding a D-FF and then applying the output of the D-FF to the reset input of the FF that forms a counter. CONSTITUTION:When the input pulse is applied through the terminal 1, FF1-FFn are turned on and off repetitively. Then NAND gate 3 is set at a low level when FF2-FFn are all set at a high level. In this case, if a fall is caused to the input signal, the D-FF reads the NAND output to turn to a low level. Thus the R signal is supplied to all FFs to start a resetting action. Then FF2-FFn are preset at the values designated by P2-Pn. And either one of P2-Pn is at a low level and read into the FF, and thus the output of the gate 3 is turned to a high level. When a fall occurs to the next input signal, the output of the gate 3 is read into the D-FF. Thus the D-FF turns to a high level to cancel the resetting action form. As a result, a delay equivalent to two units of FF has just to be given within an input period for the maximum operation speed. Thus a high speed and low power consumption can be realized.

7. 发明专利

JPS55161406A THREEETERMINAL CURRENT AMPLIFIER 失效
公开(公告)号：JPS55161406A
公开(公告)日：1980-12-16
申请号：JP6900079
申请日：1979-06-04
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： AKAZAWA YUKIO , SUDOU TSUNETAKA , NISHINO YUTAKA , MURATA MASANORI , ITOU MITSUTOSHI
IPC分类号： H03F3/343 , H03F1/34 , H03F3/34 , H03F3/347 , H04M1/26
摘要： PURPOSE:To improve stability by enlarging the open loop gain with the three-stage current amplifying constitution to enlarge the negative feedback quantity dependent upon resistances. CONSTITUTION:Three-stage current amplification of transistors Q1, Q2 and Q3 is performed, and the open loop gain is enlarged to apply the large quantity of negative feedback dependently upon resistances R1 and R2. The current gain of the amplifying circuit is determined by the ratio of values of resistances R1 and R2 approximately if emitter ground amplification factors of transistors Q1, Q2 and Q3 are sufficiently larger than 1, and this current value is not dependent upon various characteristic constants of transistors.

8. 发明专利

JPS55124822A CONSTANT VOLTAGE CIRCUIT 失效
公开(公告)号：JPS55124822A
公开(公告)日：1980-09-26
申请号：JP3219079
申请日：1979-03-22
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： NISHINO YUTAKA , YOSHIRI MAKOTO , MURATA MASANORI , ITOU MITSUTOSHI
IPC分类号： G05F1/613 , G05F3/16 , G05F3/22
摘要： PURPOSE:To sufficiently decrease the operation resistor of two terminal constant voltage circuit from small current area with a simple circuit. CONSTITUTION:In Figure, the output voltage V0 is expressed in equation 1 and it can be set to an arbitrary value by suitably selecting R1/R2. The circuit current I0 is as in equation 2, by taking the emitter currents of Q1, Q2 as IE1, IE2 and the voltage between emitter and base as VBE1, VBE2 respectively. The operating resistor r is expressed in equation 3 with re1=DELTAVBE1/DELTAIE1, re2=DELTAVBE2/DELTAIE2 and re1

9. 发明专利

JPH0218784B2 失效
公开(公告)号：JPH0218784B2
公开(公告)日：1990-04-26
申请号：JP8527583
申请日：1983-05-16
申请人： NIPPON ELECTRIC CO
发明人： MURATA MASANORI
IPC分类号： H04M1/50 , H04M1/76

10. 发明专利

JPS58172009A ACTIVE FILTER 失效
公开(公告)号：JPS58172009A
公开(公告)日：1983-10-08
申请号：JP5488782
申请日：1982-04-02
申请人： NIPPON ELECTRIC CO
发明人： MURATA MASANORI
IPC分类号： H03H11/12
摘要： PURPOSE:To vary only a center frequency on single power source driving basis through an external resistance by connecting inphase inputs of respective operational amplifiers of an active filter consisting of one adder and two integrators using the operational amplifiers to a power source through resistances. CONSTITUTION:The adder consisting of an operational amplifier 1 and resistances R4 and R8, the 1st integrator consisting of an operational amplifier 2, a capacitor C1, and a resistance R1, and the 2nd integrator consisting of an operational amplifier 3, a capacitor C2, and a resistace R2 are cascaded; the output of the 1st integrator is connected to the in-phase input of the amplifier 1 through a resistance R6 and the output of the 2nd integrator is connected to the out-of- phase input of the amplifier 1 through a resistance R to constitute the active filter. A voltage divided through resistances Ra and Rb is connected in common to the respective inphase inputs of the amplifiers 1-3 through a resistance Rc. The resistances R1 and R2 are varied simultaneously while their ratio is held constant to vary only the center frequency, holding the gain and Q constant. Further, a resistance R3 is connected in series to the C2 to compensate the excessive phase rotation of a loop, obtaining original transfer characteristics.

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