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1. 发明专利

JP2011029466A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011029466A
公开(公告)日：2011-02-10
申请号：JP2009174894
申请日：2009-07-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KITAZAWA KEIGO , NOGUCHI JUNJI , OSHIMA TAKAFUMI , WADA SHINICHIRO , MIYOSHI TOMOYUKI , ITO ATSUSHI
IPC分类号： H01L29/786 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0692 , H01L29/41758 , H01L29/42364 , H01L29/42372 , H01L29/4238
摘要： PROBLEM TO BE SOLVED: To provide a high breakdown voltage LDMOS improved in off-state breakdown performance which has been deteriorated by DCBL stress in the past. SOLUTION: The high breakdown voltage LDMOS is a MOS transistor formed on a semiconductor substrate, wherein elements are isolated by trenches and a source region is held between drain regions. A metal layer gate interconnection connected to a gate electrode is extracted out of the trenches so that it may pass through over a P-type drift layer. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供在过去的DCBL应力已经劣化的截止击穿性能方面提高的高耐压LDMOS。解决方案：高击穿电压LDMOS是形成在半导体衬底上的MOS晶体管，其中元件通过沟槽隔离，并且源极区域保持在漏极区域之间。从沟槽中提取连接到栅电极的金属层栅极互连，从而可以穿过P型漂移层。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2011238771A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011238771A
公开(公告)日：2011-11-24
申请号：JP2010108904
申请日：2010-05-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYOSHI TOMOYUKI , WADA SHINICHIRO , OSHIMA TAKAFUMI , YANAGIDA YOHEI , FUJITA TAKAHIRO
IPC分类号： H01L29/861 , H01L29/78
CPC分类号： H01L29/7836 , H01L29/0692 , H01L29/8611
摘要： PROBLEM TO BE SOLVED: To provide a high breakdown voltage diode structure which has high reverse recovery capability and a high allowable forward current.SOLUTION: A distance d between an end in a longitudinal direction of a p-well layer 8 within an anode region and an element isolation region 10 formed so as to surround a diode is set to 5 μm or less, where a depletion layer extends to the element isolation region 10 when a maximum rating reverse voltage is applied. At the end of the p-well layer 8 during recovery in the reverse direction, the electric field intensity is reduced, a hole current is suppressed and the local temperature rise is suppressed.
摘要翻译：要解决的问题：提供具有高反向恢复能力和高允许正向电流的高击穿电压二极管结构。解决方案：在阳极区域内的p阱层8的纵向方向上的端部与形成为围绕二极管的元件隔离区域10之间的距离d设定为5μm以下，其中，当施加最大额定反向电压时，层延伸到元件隔离区域10。在反向恢复期间的p阱层8的端部，电场强度降低，空穴电流被抑制并且局部温度升高被抑制。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2011124397A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011124397A
公开(公告)日：2011-06-23
申请号：JP2009281116
申请日：2009-12-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYOSHI TOMOYUKI , WADA SHINICHIRO , YANAGIDA YOHEI
IPC分类号： H01L29/861 , H01L21/329 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/94
CPC分类号： H01L29/8611 , H01L27/0255 , H01L27/0629 , H01L29/0692 , H01L29/402 , H01L29/42368 , H01L29/66128 , H01L29/66136 , H01L29/66681 , H01L29/7816
摘要： PROBLEM TO BE SOLVED: To provide a high breakdown voltage ESD protection diode which can be formed using the same manufacturing process as for the high breakdown voltage transistor to be protected with the high avalanche resistance.
SOLUTION: On the substrate surface of a PN junction formed from an N-type low concentration semiconductor substrate 1 which constitutes a cathode region 8 and a P-type low concentration diffusion region 14 which constitutes an anode region 7, a gate oxide film 12 is formed, wherein its structure is characterized in that a gate electrode 13 provided over the gate oxide film 12 and a field oxide film 4 is electrically connected to an anode electrode 20 through a gate plug 28, thereby an electric field in a PN junction is reduced at the time of avalanche breakdown to obtain the high avalanche resistance. Moreover, by changing the length of the field oxide film 4, the breakdown voltage can be adjusted.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供高耐压ESD保护二极管，其可以使用与用于高耐雪崩电阻保护的高耐压晶体管相同的制造工艺来形成。解决方案：在由构成阴极区8的N型低浓度半导体衬底1和构成阳极区7的P型低浓度扩散区14形成的PN结的衬底表面上，形成栅极氧化物形成膜12，其特征在于，设置在栅氧化膜12上的栅电极13和场氧化膜4通过栅极插塞28与阳极电极20电连接，由此PN中的电场在雪崩击穿时减少接头，以获得高雪崩阻力。此外，通过改变场氧化膜4的长度，可以调节击穿电压。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2010080803A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010080803A
公开(公告)日：2010-04-08
申请号：JP2008249506
申请日：2008-09-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYOSHI TOMOYUKI , WADA SHINICHIRO , YANAGIDA YOHEI
IPC分类号： H01L27/08 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L29/78
CPC分类号： H01L27/0664 , H01L29/7393 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To achieve reduction in cell size and improvement of reliability with respect to a semiconductor device having a plurality of transistors constituting a multi-channel output circuit.
SOLUTION: In multi-channel circuit constitution, a group of transistors of a plurality of channels having a common function is enclosed with a common trench to be isolated by an insulating element from a transistor group having a different function, collector parts of adjacent high-side transistors are connected to a VH power source in common, and emitter parts of a transistor group of adjacent low-side channels are connected to a GND power source in common.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：相对于具有构成多通道输出电路的多个晶体管的半导体器件，实现电池尺寸的减小和可靠性的提高。解决方案：在多通道电路结构中，具有共同功能的多个通道的一组晶体管被公共沟槽包围，以由绝缘元件与具有不同功能的晶体管组隔离，集电器部分相邻的高侧晶体管共同连接到VH电源，相邻的低侧通道的晶体管组的发射极部分共同地连接到GND电源。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2015026751A 横型バイポーラトランジスタおよびその製造方法审中-公开
标题翻译：横向双极晶体管及其制造方法
公开(公告)号：JP2015026751A
公开(公告)日：2015-02-05
申请号：JP2013156250
申请日：2013-07-29
申请人：株式会社日立製作所 , Hitachi Ltd
发明人： MIYOSHI TOMOYUKI , OSHIMA TAKAFUMI , YANAGIDA YOHEI
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L29/7394 , H01L29/0821 , H01L29/1008 , H01L29/6625 , H01L29/66325 , H01L29/735 , H01L29/7816
摘要：【課題】微細CMOSFET,LDMOSFETと混載できる横型バイポーラトランジスタにおいて、製造ばらつきの影響を受け難く、高いゲインを有するトランジスタ構造、製造方法を提供する。【解決手段】横型バイポーラトランジスタは、ゲート電極33に対し自己整合的に不純物打ち込み、拡散によりベース層30及びエミッタ層29を形成する製造工程と構造を有する。さらに、ゲート電極を、ベース40、エミッタ42、コレクタ44に加え、独立した第4番目の端子として利用する事で、与えたゲート電位により、hfeを制御、向上できる。以上より、製造ばらつきの影響を受け難い、もしくは、ゲート端子により補正可能な、高いゲイン有するバイポーラトランジスタを提供できる。【選択図】図16
摘要翻译：要解决的问题：为了提供不太可能受到制造变化和高增益影响的横向双极晶体管的结构，水平双极晶体管能够与精细CMOSFET和LDMOSFET混合安装，以及制造方法横向双极晶体管。解决方案：横向双极晶体管具有制造步骤和通过以自对准将杂质注入到栅电极33中而形成基极层30和发射极层29的结构，以扩散。此外，除了基极40，发射极42和集电极44之外，栅极用作独立的第四端子，从而可以通过施加的栅极电位来控制和增加hfe。因此，可以提供一种不太可能受制造变化影响或能够被栅极端子校正并且具有高增益的双极晶体管。

6. 发明专利

JP2015032767A 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：JP2015032767A
公开(公告)日：2015-02-16
申请号：JP2013162946
申请日：2013-08-06
申请人：株式会社日立製作所 , Hitachi Ltd
发明人： KIMURA HIROKI , YANAGIDA YOHEI , MIYAKOSHI KENJI , MIYOSHI TOMOYUKI , OSHIMA TAKAFUMI
IPC分类号： H01L21/8234 , H01L21/822 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/786
CPC分类号： H01L27/0255 , H01L27/0259 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要：【課題】静電保護素子のESD耐量を向上する。【解決手段】、基本思想の本質は、静電保護素子ESDとして、ダイオードと並列接続するように、サイリスタやnpnバイポーラトランジスタではなく、pnpバイポーラトランジスタを含むように構成する点にある。言い換えれば、基本思想の本質は、pnpバイポーラトランジスタが寄生的に設けられたダイオードから静電保護素子ESDを構成する点にあるともいえる。【選択図】図6
摘要翻译：要解决的问题：提高静电保护元件的ESD抗扰度。解决方案：基本思想的本质是配置为不使用晶闸管或npn双极晶体管，而是包含pnp双极晶体管作为静电保护元件ESD 并与二极管并联连接。换句话说，基本思想的本质是构成一个配有pnp双极晶体管的二极管的静电保护元件ESD。

7. 发明专利

JP2014165293A Field-MOSFET AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：现场MOSFET及其制造方法
公开(公告)号：JP2014165293A
公开(公告)日：2014-09-08
申请号：JP2013034122
申请日：2013-02-25
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYOSHI TOMOYUKI , OSHIMA TAKAFUMI , TOMINARI TATSUYA , HAYASHI MASAHIRO
IPC分类号： H01L21/336 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To improve the reduction phenomenon of breakdown voltage and the NBTI deterioration phenomenon at a gate voltage high slew rate, triggered by the carrier trap to an oxide film, in a Field-MOSFET composed by using a field oxide film as a gate insulating film.SOLUTION: A Field-MOSFET includes a field oxide film provided selectively on the surface of a semiconductor region existing on a semiconductor substrate, a p-type drain region provided in the vicinity of the field oxide film and having a p-type feed region, a p-type source region provided in the vicinity of the field oxide film and having a p-type feed region, and a gate electrode provided via a field oxide film so as to face a well region. A carrier trap existing parasitically in the field oxide film, reaching the source region from under the gate electrode, especially in the vicinity of the boundary surface to silicon, is terminated with an ion.
摘要翻译：要解决的问题：为了提高在通过使用场氧化膜作为氧化膜形成的场MOSFET中的由栅极电压高压摆率引起的击穿电压和NBTI劣化现象，由载流子阱触发到氧化膜栅极绝缘膜。解决方案：场MOSFET包括选择性地设置在存在于半导体衬底上的半导体区域的表面上的场氧化膜，设置在场氧化膜附近的p型漏区，设置在场氧化膜附近并具有p型馈电区域的p型源区，以及经由场氧化膜设置以面对阱区的栅电极。寄生在现场氧化膜中的载流子阱，由栅电极下面，特别是在界面附近到达硅的区域到达源区，用离子终止。

8. 发明专利

JP2014011411A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014011411A
公开(公告)日：2014-01-20
申请号：JP2012149002
申请日：2012-07-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYOSHI TOMOYUKI , OSHIMA TAKAFUMI , YANAGIDA YOHEI , KIMURA HIROKI , MIYAKOSHI KENJI
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78 , H01L29/786 , H01L29/861 , H01L29/868
CPC分类号： H01L29/7818 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/42368 , H01L29/7816 , H01L29/7819 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To reduce adverse effects on current performance of an LDMOSFET, to suppress a carrier injection amount from an anode layer of an LDMOS parasitic diode, and to improve reverse direction recovery resistance of the parasitic diode.SOLUTION: A disclosed LDMOSFET comprises: a semiconductor substrate which is configured by selectively forming a field oxide film on a surface layer of a semiconductor region and includes a first semiconductor region formed from a first conductive type feed region, a second conductive type well region to be an opposite conductive type and a second semiconductor region formed from a first conductive type feed region and a second conductive type feed region formed on an upper layer of the second conductive type well region on a position on which the field oxide film does not exist; and a gate electrode arranged oppositely to the well region through the gate oxide film. The feed regions are formed with distances from the field oxide film on their longitudinal direction end parts, and preferably the feed regions are intermittently formed with a predetermined interval in a longitudinal direction and the feed regions are applied to the first semiconductor region.
摘要翻译：要解决的问题：减少对LDMOSFET的电流性能的不利影响，以抑制来自LDMOS寄生二极管的阳极层的载流子注入量，并改善寄生二极管的反向恢复电阻。解决方案：所公开的LDMOSFET包括：半导体衬底，其通过在半导体区域的表面层上选择性地形成场氧化物膜而构成，并且包括由第一导电型馈电区域形成的第一半导体区域，与另一导电类型相对的第二导电类型阱区域，以及由不存在所述场氧化膜的位置上形成于所述第二导电型阱区的上层的第一导电型馈电区域和第二导电型馈电区域形成的第二半导体区域; 以及通过栅极氧化物膜与阱区域相对布置的栅电极。馈电区域在其纵向端部形成有距离场氧化膜的距离，并且优选地，馈送区域在纵向方向上以预定间隔间歇地形成，并且馈送区域被施加到第一半导体区域。

9. 发明专利

JP2010238839A Lateral insulated-gate bipolar transistor, and method of manufacturing the same 有权
标题翻译：横向绝缘门双极晶体管及其制造方法
公开(公告)号：JP2010238839A
公开(公告)日：2010-10-21
申请号：JP2009083966
申请日：2009-03-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYOSHI TOMOYUKI , WADA SHINICHIRO , YANAGIDA YOHEI
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a lateral insulated-gate bipolar transistor having a plurality of channels, capable of suppressing sacrifice such as deterioration of current performance, and materializing improvement of latch-up resistance.
SOLUTION: A base region (channel region) formed by intermittently processing a gate electrode 14 coming closest to a collector is intermittently changed to suppress occurrence of latch-up in the vicinity of the proximate channel region which determines latch-up resistance of an element. A second conductivity type base leading-out region is formed in the recessed portion of the processed most proximate gate electrode, in an emitter region, and thereby, the portion (the region) exhibits hole extraction effect, and further improvement of latch-up resistance can be expected.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供具有多个通道的横向绝缘栅双极晶体管，能够抑制诸如电流性能劣化的牺牲，并且实现闩锁电阻的提高。解决方案：通过间歇地处理最接近集电极的栅电极14形成的基极区（沟道区）被间歇地改变，以抑制确定闭锁电阻的邻近沟道区附近的闩锁的发生一个元素在发射极区域中，在处理最近的栅电极的凹部形成第二导电型基极引出区域，从而部分（区域）显示出空穴提取效应，进一步提高闩锁电阻可以预料。版权所有（C）2011，JPO＆INPIT

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