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1. 发明专利

JPH10154900A METHOD AND SYSTEM FOR ANALYZING FAILURE OF PRINTED BOARD FOR MOUNTING ELECTRONIC DEVICE 失效
公开(公告)号：JPH10154900A
公开(公告)日：1998-06-09
申请号：JP31341596
申请日：1996-11-25
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： OCHIAI TATSUO , TABUCHI HIDEKI , YAMADA YU , KUWABARA YOSHIHIRO , MOGI KEIJI
IPC分类号： H05K13/08 , G05B13/02 , G05B23/02
摘要： PROBLEM TO BE SOLVED: To reduce labor required for failure analysis or preparation thereof by making the input layer of a neural network to correspond with test items of test results for a printed board and making the output layer to correspond with the failure index of devices mounted on the printed board thereby estimating a failed device. SOLUTION: A neural network 110 comprises a hierarchical feedforward network including an input layer 111, an intermediate layer 112 and a output layer 113 wherein engineeringly simulated neural cells, i.e., neurons 114-116, are information processing units. One-and-one correspondence is present between each neuron 114 constituting the input layer 111 of the neural network 110 and each item in the item column 102 of test result list 101 of a printed board for mounting electronic devices. A failed device is estimated by making each neuron 116 constituting the output layer 113 of the neural network 110 to correspond with each number in the number column 121 of analyzed parts list 120 of the printed board for mounting electronic devices.

2. 发明专利

JPH0581062A BOARD DIAGNOSTIC EXPERT SYSTEM 失效
公开(公告)号：JPH0581062A
公开(公告)日：1993-04-02
申请号：JP24310691
申请日：1991-09-24
申请人： HITACHI LTD
发明人： TABUCHI HIDEKI , YAMADA YU
IPC分类号： G06F11/22 , G06F9/44
摘要： PURPOSE:To automatically synthesize an expert system which analyzes and supports the fault of a board from various data bases. CONSTITUTION:The fault analysis procedure of the whole board is synthesized in a synthesis means 3 based on a check method for recognizing the normality of parts carriers stored in a parts data base 2, parts which are stored in a board parts data base 1 and constitute the board related to a test item and priority showing the order of the suspicion of the parts. The analysis procedure is stored in a knowledge base 4 and the board is diagnosed by an inference mechanism 6.

3. 发明专利

JPH01263575A METHOD FOR TESTING ELECTRONIC CIRCUIT 失效
公开(公告)号：JPH01263575A
公开(公告)日：1989-10-20
申请号：JP9132688
申请日：1988-04-15
申请人： HITACHI LTD
发明人： TABUCHI HIDEKI
IPC分类号： G01R31/28
摘要： PURPOSE:To rapidly confirm the functions of many electronic circuits even when said electronic circuits are mounted on a board, by sending out a judge result to a tester from a microcomputer as a test result after the testing of all of the electronic circuits is finished. CONSTITUTION:Electronic circuits 3-2{-(1-N)} and a microcomputer 3-1 for controlling respective circuits are mounted on an electronic circuit mounting board 3. A CPU as a tester 1 converts a series signal to a parallel signal through a signal converter circuit 2 to send the same to the microcomputer 3-1 or the contrarily send out the same. Next, a test mode is set on the basis of a test order by the computer 3-1 to process a switching test routine 12. When the test order is received by a test order receiving processor 12-1, the circuits 3-2 are selected in predetermined order by an electronic circuit selecting/test order selecting processor 12-2, a response receiving processor 12-3 and an acceptability judge processor 12-4 to send out said order and response is received to be compared with an expected value to judge whether said response is acceptable. When the results of all of the circuits are obtained, these judges are sent out to a usual processing routine 11 as test results from the computer 3-1 by a test result send-out processor 12-5 through the circuit 2.

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