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1. 发明专利

JPS59165159A Monitoring device for system operation 失效
标题翻译：监控系统运行的装置
公开(公告)号：JPS59165159A
公开(公告)日：1984-09-18
申请号：JP3967383
申请日：1983-03-10
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： HONDA TAKASHI , OOYAMA SHIGERU , ARIMA SHIYUUHEI
IPC分类号： G06F11/28 , G06F11/30
CPC分类号： G06F11/3024 , G06F11/3096
摘要： PURPOSE:To obtain the instantaneousness and flexibility of monitoring and to reduce the load on hardware by reading a monitor operation instruction out of a slave memory and executing it when a specific address of a main processor is accessed or when a specific instruction is executed. CONSTITUTION:For example, a monitor operation instruction to be executed when an address in a main memory is accessed is stored in an address A' of the slave memory 20. Further, a monitor operation instruction to be executed when an address N of the main memory is accessed is stored in an address N' of the slave memory 20. Therefore, when the address A is accessed, the address A' of the slave memory is accessed and the instruction stored therein is read out to a processor 21 for monitor operation. Similarly, when the address N is accessed, the address N' of the slave memory 20 is accessed to read its stored instruction out to the processor 21. The processor 20 receiving the instruction uses its various incorporated registers, arithmetic logical device, and an additional memory 22 to carry out specific monitor operation.
摘要翻译：目的：为了获得监控的瞬时性和灵活性，并通过读取从属存储器中的监视器操作指令并在访问主处理器的特定地址或执行特定指令时执行监视操作指令来减少硬件负载。构成：例如，当访问主存储器中的地址时要执行的监视器操作指令被存储在从存储器20的地址A'中。此外，当主存储器20的地址N被执行时，执行监视操作指令存储器被存储在从存储器20的地址N'中。因此，当访问地址A时，访问从存储器的地址A'，并将其中存储的指令读出到处理器21进行监视操作。类似地，当访问地址N时，从存储器20的地址N'被访问以将其存储的指令读出到处理器21.接收指令的处理器20使用其各种并入的寄存器，算术逻辑器件和附加存储器22进行特定的监视操作。

2. 发明专利

JPS59111456A Charging system in communication between telephone network and different kind of network 失效
标题翻译：电话网络与网络不同种类之间通信的充电系统
公开(公告)号：JPS59111456A
公开(公告)日：1984-06-27
申请号：JP22114582
申请日：1982-12-17
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： ARIMA SHIYUUHEI , KADOTA MITSUHIRO , HOSHIDA KATSUNORI , OOYAMA SHIGERU
IPC分类号： H04M15/00
CPC分类号： H04M15/00
摘要： PURPOSE:To charge the sum of fees of both networks to a subscriber of a telephone network by providing a gate device converting the interface between the telephone network and a different kind of network to count the charge of both the networks. CONSTITUTION:Information of a subscriber is transmitted and received between exchanges 14 and 16 via a route of common line signals 18, 19. An old type exchange 8 decides the range depending on the incoming address, selects a metering pulse corresponding to the range and transmits the pulse to a subscriber exchange 8. The pulse is counted by a metering pulse counter 7, the number of metering pulses of every month is calculated and a charge is requested to the subscriber. The gate device 11 is positioned between the telephone network and the different kind of network, and interfaces with both the networks in matching with the interface condition.
摘要翻译：目的：通过提供转换电话网络和不同类型的网络之间的接口的门设备来计算两个网络的费用，来向两个网络的用户收取两个网络的费用的总和。构成：通过公共线路信号18,19的路径在交换机14和16之间发送和接收用户的信息。旧式交换机8根据输入地址决定该范围，选择与该范围对应的计量脉冲并发送到订户交换的脉冲8.脉冲由计量脉冲计数器7计数，计算每月的计数脉冲数，并向用户请求电荷。门设备11位于电话网络和不同类型的网络之间，并且与接口条件匹配的两个网络接口。

3. 发明专利

JPS592134A Bus interface circuit of communication control device 失效
标题翻译：通信控制设备的总线接口电路
公开(公告)号：JPS592134A
公开(公告)日：1984-01-07
申请号：JP11134182
申请日：1982-06-28
申请人： Nippon Telegr & Teleph Corp
发明人： TOBE YOSHIHARU , YASHIRO ZENICHI , OOYAMA SHIGERU
IPC分类号： H04L29/10 , G06F13/00 , G06F13/28 , G06F13/42
CPC分类号： G06F13/4239
摘要： PURPOSE:To reduce the kinds of IC to one kind, by constituting a bus interface circuit by use of the number of blocks for bit-slicing it to the same function unit consiting of a latching circuit, a bus controlling circuit and a selecting circuit. CONSTITUTION:A (write) circuit control part instructs write to a circuit 7 through a control line 8, divides a write address into two and loads it one a common bus. It is latched by a latching circuit and is loaded on an address bus 5. Subsequently, a write data is divided into two, is loaded on a bus 4 and is loaded on a data bus 6 through the latching circuit. A memory write line 12 is selected by a selector, and a main memory is subjected to access. In this way, a bus interface circuit is divided into plural function units having the same circuit configuration, and can be converted to an IC by a function unit, and it can be obtained at a low cost by using plural ICs of only one kind of the bus interface circuit.
摘要翻译：目的：为了将IC的种类减少到一种，通过使用用于对与锁存电路相同的功能单元进行位片分割的块数构成总线接口电路，总线控制电路和选择电路。构成：（写入）电路控制部分通过控制线8指示对电路7的写入，将写入地址分成两部分，并将一个公共总线加载。它由锁存电路锁存，并被加载到地址总线5上。随后，写入数据被分成两部分，被加载在总线4上，并通过锁存电路被加载到数据总线6上。存储器写入线12由选择器选择，并且主存储器被访问。以这种方式，总线接口电路被分成具有相同电路结构的多个功能单元，并且可以通过功能单元转换为IC，并且可以通过使用仅一种的多个IC来以低成本获得总线接口电路。

4. 发明专利

JPS59172047A Processor additional device 失效
标题翻译：处理器附加设备
公开(公告)号：JPS59172047A
公开(公告)日：1984-09-28
申请号：JP4604283
申请日：1983-03-22
申请人： Nippon Telegr & Teleph Corp
发明人： HONDA TAKASHI , OOYAMA SHIGERU , ICHIKAWA HIROYUKI
IPC分类号： G06F11/34 , G06F15/16 , G06F15/177
CPC分类号： G06F11/34
摘要： PURPOSE:To detect many address passages with a small-sized circuit constitution by utilizing a PLA (programmable logic array) element as an address information coincidence detecting circuit. CONSTITUTION:Address data is inputted to an input information latch register 20 of the PLA by an address output timing extracting circuit 18. Its information is compared with plural trigger address groups which are preliminarily programmed in an AND array part 21. If a programmed trigger address coincides with input address data, the signal is sent to an OR array part 22. Counter number information of the OR array part 22 is inputted together with an interrupt signal 26 to an attached processor 24 which executes the postprocessing. On the side of the attached processor 24, the counter number is inputted when the interrupt signal 26 is inputted. Then, a counter set in a memory 25 of the processor 24 itself is counted up.
摘要翻译：目的：通过利用PLA（可编程逻辑阵列）元件作为地址信息符合检测电路来检测具有小尺寸电路结构的许多地址段。构成：地址数据由地址输出定时提取电路18输入到PLA的输入信息锁存寄存器20中。其信息与在AND阵列部分21中预先编程的多个触发地址组进行比较。如果编程的触发地址与输入地址数据一致，信号被发送到OR阵列部分22.或者将数组部分22的计数器信息与中断信号26一起输入到执行后处理的附加处理器24。在附加处理器24侧，输入中断信号26时输入计数器号。然后，计数器设置在处理器24本身的存储器25中。

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