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    • 1. 发明专利
    • Thermal stress analysis method of electronic component and resin flow analysis method
    • 电子元件和树脂流动分析方法的热应力分析方法
    • JP2010108150A
    • 2010-05-13
    • JP2008278269
    • 2008-10-29
    • Elpida Memory IncHitachi Ltdエルピーダメモリ株式会社株式会社日立製作所
    • KONO TSUTOMUMINO MASAYUKITAKESHIMA HIDEHIROITO HIROYUKIGOI TOMOKO
    • G06F17/50B29C45/76
    • G01N3/00G01N2203/0214
    • PROBLEM TO BE SOLVED: To evaluate a curvature deformation amount by taking a relationship between a filling rate and a linear expansion coefficient of fillers filled in a resin into account in a resin in a resin filling process of a package. SOLUTION: A thermal stress analysis method of an electronic component performs a resin flow analysis by filling particles simulating fillers in a resin to calculate a filler filling rate at every spot in a package. Here, the method converts the filler filling rate at every spot into a linear expansion coefficient by using a database in which the filler filling rate and the linear expansion coefficient are experimentally calculated. The method can predict a curvature deformation amount by means of a structure analysis taking a linear expansion coefficient obtained from a distribution of the filler filling rates in the package into account by using the converted linear expansion coefficient as an input value for a thermal stress analysis. Further, after calculating a curvature deformation amount of a semiconductor package having a sheet shape in the manner, the method calculates curvature deformation amounts of individual packages by dividing the package into the respective substrate areas in which each chip operates electrically. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:通过在包装的树脂填充过程中考虑在树脂中填充的填料的填充率和线膨胀系数之间的关系来评估曲率变形量。 解决方案:电子部件的热应力分析方法通过将模拟填料的颗粒填充到树脂中来计算填料中每个点的填充剂填充率来进行树脂流动分析。 这里,通过使用实验计算填充填充率和线膨胀系数的数据库,将各点的填充填充率变换为线膨胀系数。 该方法可以通过使用由转换的线性膨胀系数作为热应力分析的输入值而考虑从包装中的填料填充率的分布获得的线性膨胀系数的结构分析来预测曲率变形量。 此外,在以这种方式计算具有片状的半导体封装的曲率变形量之后,该方法通过将封装分成其中每个芯片电连接的各个衬底区域来计算各个封装的曲率变形量。 版权所有(C)2010,JPO&INPIT
    • 2. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2011233610A
    • 2011-11-17
    • JP2010100541
    • 2010-04-26
    • Elpida Memory Incエルピーダメモリ株式会社
    • GOI TOMOKO
    • H01L23/12
    • H01L2224/73265H01L2924/15311H01L2924/181H01L2924/00012
    • PROBLEM TO BE SOLVED: To provide a semiconductor device having reduced thickness and preventing an occurrence of warpage accompanied by the reduction.SOLUTION: A semiconductor device 10 comprises a semiconductor chip 11, a wiring board 12, and an encapsulation resin 15. The wiring board has a first solder resist on a semiconductor chip-mounting surface on which the semiconductor chip is mounted. The encapsulation resin seals the semiconductor chip mounted on the semiconductor chip-mounting surface. The region on the semiconductor chip-mounting surface on which the semiconductor chip is mounted is a non-coated region in which the first solder resist is not provided.
    • 要解决的问题:提供一种具有减小的厚度并防止伴随着还原的翘曲发生的半导体器件。 解决方案:半导体器件10包括半导体芯片11,布线板12和封装树脂15.布线板在安装半导体芯片的半导体芯片安装表面上具有第一阻焊剂。 封装树脂密封安装在半导体芯片安装表面上的半导体芯片。 安装半导体芯片的半导体芯片安装表面上的区域是不设置第一阻焊剂的未涂覆区域。 版权所有(C)2012,JPO&INPIT