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1. 发明公开

EP3787998A1 A METHOD FOR SELECTIVE INCORPORATION OF DOPANT ATOMS IN A SEMICONDUCTIVE SURFACE 有权转让
公开(公告)号：EP3787998A1
公开(公告)日：2021-03-10
申请号：EP19796207.9
申请日：2019-05-02
申请人： Newsouth Innovations Pty Ltd
发明人： SIMMONS, Michelle , KEIZER, Joris
IPC分类号： B82Y10/00 , G06N10/00 , H01L21/18 , B82Y30/00 , G01Q80/00 , H01L29/02

2. 发明公开

EP3459117A1 METHOD OF FORMING A P-TYPE LAYER FOR A LIGHT EMITTING DEVICE 有权
公开(公告)号：EP3459117A1
公开(公告)日：2019-03-27
申请号：EP17799903.4
申请日：2017-05-11
申请人： Lumileds LLC
发明人： WILDESON, Isaac , NELSON, Erik Charles , DEB, Parijat
IPC分类号： H01L29/02 , H01L21/306 , H01L21/02 , H01L21/324

3. 发明公开

EP2926375A1 INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR PRODUCING THE SAME 审中-公开
标题翻译：集成电路与系统和方法及其生产
公开(公告)号：EP2926375A1
公开(公告)日：2015-10-07
申请号：EP13857801.8
申请日：2013-11-21
申请人： Intel Corporation
发明人： NIKONOV, Dmitri E. , SANKMAN, Robert L. , KIM, Raseong , PAN, Jin
IPC分类号： H01L29/02
CPC分类号： H05K3/4644 , B29C64/00 , B32B27/06 , B32B2457/00 , B33Y50/02 , B33Y70/00 , B33Y80/00 , H01L27/0688 , H01L27/281 , H01L51/0004 , H05K1/00
摘要： Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.
摘要翻译：包括半导电有机材料的三维集成电路中描述。在一些实施例中，三维集成电路包括一个或多个电子元件确实包括形成一个或多个有机半导体材料的半导体区域。因此，三维集成电路的电子元件可包括绝缘的有机绝缘材料形成的区域，并且导电区域由导电材料形成。如三维印刷：所述三维集成电路可以在添加制造工艺形成由。因此装置和用于产生和检测三维集成电路的方法进行说明。

4. 发明公开

EP2412012A4 STRUCTURE AND FABRICATION OF ASYMMETRIC FIELD-EFFECT TRANSISTOR HAVING ASYMMETRIC CHANNEL ZONE AND DIFFERENTLY CONFIGURED SOURCE/DRAIN EXTENSIONS 审中-公开
标题翻译：设计和不对称场效应晶体管不对称沟道区域的制造及不同配置的源/漏扩展
公开(公告)号：EP2412012A4
公开(公告)日：2014-03-05
申请号：EP10756487
申请日：2010-03-25
申请人： NAT SEMICONDUCTOR CORP
发明人： BULUCEA CONSTANTIN , FRENCH WILLIAM D , BAHL SANDEEP R , YANG JENG-JIUN , PARKER D COURTNEY , JOHNSON PETER B , ARCHER DONALD M
IPC分类号： H01L21/70 , H01L29/02 , H01L29/10
CPC分类号： H01L29/7835 , H01L21/26586 , H01L21/82285 , H01L21/823807 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L27/0922 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/167 , H01L29/66659
摘要： An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.

5. 发明公开

EP2642341A2 Manufacturing method of an apparatus for the processing of single molecules 审中-公开
标题翻译：一种用于制造一种用于单个分子的处理方法
公开(公告)号：EP2642341A2
公开(公告)日：2013-09-25
申请号：EP12174261.3
申请日：2012-06-29
申请人： Koninklijke Philips N.V.
发明人： The designation of the inventor has not yet been filed
IPC分类号： G03F7/00 , H01L29/02 , B82Y15/00
CPC分类号： G01N33/48721 , B81C1/00087 , B81C2201/0149 , B82Y30/00 , G03F7/0002
摘要： The invention relates to a method for manufacturing an apparatus for the processing of single molecules. According to this method, a self-assembling resist (155) is deposited on a processing layer (110, PL) and allowed to self-assemble into a pattern of two phases (155a, 155b). One of these phases (155a) is then selectively removed, and at least one aperture is generated in the processing layer (110, PL) through the mask of the remaining resist (155b). Thus apertures of small size can readily be produced that allow for the processing of single molecules (M), for example in DNA sequencing.
摘要翻译：本发明涉及一种用于制造装置的单个分子的处理的方法。。根据该方法，自组装抗蚀剂（155）沉积的处理层（110，PL）上，并使其自组装成两个相（155A，155B）的图案。一个合成相（155A）的随后选择性地去除，并通过剩余的抗蚀剂（155B）的掩模的处理层（110，PL）中产生的至少一个孔。 THUS小尺寸的孔径可以容易地制造并允许单分子（M），对于在DNA测序实施例的处理。

6. 发明公开

EP2608265A2 Semiconductor device having a gate electrode 审中-公开
标题翻译： Halbleiterbauelement mit einer Gateelektrode
公开(公告)号：EP2608265A2
公开(公告)日：2013-06-26
申请号：EP12198057.7
申请日：2012-12-19
申请人： NGK Insulators, Ltd.
发明人： Yokoi, Shoji , Shimizu, Naohiro , Kimura, Masakazu
IPC分类号： H01L29/739 , H01L29/10 , H01L29/02
CPC分类号： H01L29/74 , H01L29/1066 , H01L29/7392
摘要： A semiconductor device (10) contains a semiconductor substrate (12), a cathode (20), an anode (22), and a gate electrode (24). The semiconductor device (10) has a cathode segment (26) disposed in a portion corresponding to at least the cathode (20), an anode segment (28) disposed in a portion corresponding to the anode (22), a plurality of embedded segments (30) disposed in a portion closer to the cathode segment (26) than to the anode segment (28), a takeoff segment (32) disposed between the gate electrode (24) and the embedded segments (30) to electrically connect the gate electrode (24) to the embedded segments (30), and a channel segment (31) disposed between the adjacent embedded segments (30).
摘要翻译：半导体器件（10）包含半导体衬底（12），阴极（20），阳极（22）和栅电极（24）。半导体器件（10）具有设置在至少对应于阴极（20）的部分中的阴极段（26），设置在与阳极（22）对应的部分中的阳极段（28），多个嵌入段（30），设置在比阳极段（28）更靠近阴极段（26）的部分中;设置在栅电极（24）和嵌入段（30）之间的电流连接门电极（24）到嵌入段（30），以及设置在相邻的嵌入段（30）之间的通道段（31）。

7. 发明公开

EP2412018A1 STRUCTURE AND FABRICATION OF FIELD-EFFECT TRANSISTOR USING EMPTY WELL IN COMBINATION WITH SOURCE/DRAIN EXTENSIONS OR/AND HALO POCKET 有权
标题翻译：建设和生产的场效应晶体管的空空腔与源极/漏极扩展和/或卤素组合BAG
公开(公告)号：EP2412018A1
公开(公告)日：2012-02-01
申请号：EP10756495.7
申请日：2010-03-25
申请人： National Semiconductor Corporation
发明人： BULUCEA, Constantin , YANG, Jeng-Jiun , FRENCH, William, D. , BAHL, Sandeep, R. , PARKER, D. Courtney
IPC分类号： H01L21/70 , H01L29/02 , H01L29/10
CPC分类号： H01L29/0847 , H01L21/26513 , H01L21/2652 , H01L21/2658 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7833 , H01L29/7835
摘要： Insulated-gate field-effect transistors (IGFETs), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E). Alternatively or additionally, a more heavily doped pocket portion (250 or 290) of the body material extends along one of the source/drain zones. When present, the pocket portion typically causes the IGFET to be an asymmetric device.

8. 发明公开

EP2297782A1 NANOSTRUCTURED MEMORY DEVICE 审中-公开
标题翻译：纳米结构的存储设备
公开(公告)号：EP2297782A1
公开(公告)日：2011-03-23
申请号：EP09794734.5
申请日：2009-07-02
申请人： QuNano AB
发明人： SAMUELSON, Lars , THELANDER, Claes , OHLSSON, Jonas , MIKKELSEN, Anders
IPC分类号： H01L27/105 , H01L29/02 , H01L29/06 , H01L29/12 , H01L29/80
CPC分类号： H01L29/7881 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42332 , H01L29/66825 , H01L29/803 , Y10S977/938
摘要： The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centres (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centres (10) may be charged /written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centres (10) alters the conductivity of the nanowire (3).

9. 发明公开

EP2229696A1 INTEGRATED III-NITRIDE POWER CONVERTER CIRCUIT 审中-公开
标题翻译：集成III-NITRIDE电源转换器电路
公开(公告)号：EP2229696A1
公开(公告)日：2010-09-22
申请号：EP08724910.8
申请日：2008-01-29
申请人： International Rectifier Corporation
发明人： BAHRAMIAN, Hamid, Tomy , ZHANG, Jason , BRIERE, Michael, A.
IPC分类号： H01L29/02
CPC分类号： H02M1/08 , H03K17/04 , H03K17/06 , H03K2017/6875
摘要： An integrated circuit that includes a power stage and a driver stage, all stages using III-nitride power devices.
摘要翻译：包含功率级和驱动级的集成电路，所有级都使用III族氮化物功率器件。

10. 发明授权

EP1702365B1 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN 110 UNDER BIAXIAL COMPRESSIVE STRAIN 有权
标题翻译：提高电子和空穴迁移率，在110 SUB-双轴压缩TENSION
公开(公告)号：EP1702365B1
公开(公告)日：2009-12-02
申请号：EP04822326.7
申请日：2004-12-15
申请人： International Business Machines Corporation
发明人： CHAN, Victor , FISCHETTI, Massimo, V. , HERGENROTHER, John, M. , LEONG, Meikei , RENGARAJAN, Rajesh , REZNICEK, Alexander c/o IBM United Kingdom Ltd , SOLOMON, Paul , SUNG, Chun-Yung , YANG, Min
IPC分类号： H01L29/02 , H01L29/04 , H01L21/762
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ‘’biaxial compressive stress’’ is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

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