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1. 发明公开

EP4436101A1 VERIFICATION D'UNE DONNEE 审中-实审
公开(公告)号：EP4436101A1
公开(公告)日：2024-09-25
申请号：EP24165215.5
申请日：2024-03-21
申请人： STMicroelectronics International N.V.
发明人： PEETERS, Michael , BLANC, Pierre-Alexandre
IPC分类号： H04L9/30 , G06F7/58 , H04L9/00 , H04L9/06 , G06F7/72
CPC分类号： H04L2209/80520130101 , H04L9/004 , H04L9/0662 , H04L9/3033 , H04L9/3093 , G06F7/72 , G06F2207/720420130101 , G06F7/586
摘要： La présente description concerne un procédé de vérification d'une première donnée égale à la somme, module la dimension d'un espace comprenant ladite première donnée, de N deuxièmes données indépendantes de la première donnée, N étant un entier, comprenant une étape de vérification (404) d'une première égalité (Bj) parmi les N deuxièmes égalités données par la formule mathématique suivante : LCGk=j∗LCGMk+∑i=1NLCGXimodm dans laquelle :
- LCG( ) représente l'image d'une donnée par une fonction de génération congruentielle linéaire ;
- Xi représente l'une desdites au moins deux deuxièmes données, i variant de 1 à N ;
- N représente le nombre desdites au moins deux deuxièmes données ;
- mod( ) représente l'opérande module ;
- m représente le module de ladite fonction ;
- j est un entier variant de 0 à N-1 ; et
- dans laquelle Mk représente l'image de ladite dimension par ladite fonction.

2. 发明公开

EP4387157A1 BLINDED SEMI-STATIC ELLIPTIC CURVE DIFFIE-HELLMAN AUTHENTICATION PROTOCOL 审中-公开
公开(公告)号：EP4387157A1
公开(公告)日：2024-06-19
申请号：EP23215227.2
申请日：2023-12-08
申请人： NXP B.V.
发明人： Murray, Bruce , Lamberger, Mario
IPC分类号： H04L9/00 , G06F7/72 , H04L9/30 , H04L9/32 , H04L9/08
CPC分类号： H04L2209/80520130101 , H04L2209/04620130101 , H04L2209/0820130101 , H04L9/3218 , H04L9/3013 , H04L9/003 , H04L9/3066 , H04L9/085
摘要： Various embodiments relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for an elliptic curve cryptography authentication method based on an elliptic curve in a processor, the instructions, comprising: generating, by a verifier, a random challenge r; multiplying, by the verifier, the random challenge r by a basepoint G to produce R; sending an x coordinate of R to a prover; receiving an x-coordinate of a first point P1 and a second point P2 from the prover, wherein P1 is based on a random share q1 of the private key q of the prover and R, and wherein P2 is based on a random share q2 of the private key q and R; where q = q1 - q2, finding a point P1' on the elliptic curve having an x-coordinate of the first point P1; finding a point P2' on the elliptic curve having an x-coordinate of the second point P2; and authenticating the prover when an x-coordinate of one of P1'+P2' and P1'−P2' matches an x-coordinate of r · Q, wherein Q is a public key of the prover.

3. 发明公开

EP4307102A1 COMPUTER-IMPLEMENTED METHOD FOR DETERMINING A GAUSSIAN INTEGER CONGRUENT TO A GIVEN GAUSSIAN INTEGER MODULO A GAUSSIAN INTEGER MODULUS, METHOD FOR DETERMINING A REDUCTION OF A GIVEN GAUSSIAN INTEGER MODULO A GAUSSIAN INTEGER MODULUS AND CRYPTOGRAPHIC METHOD AND ERROR-CORRECTION METHOD 审中-公开
公开(公告)号：EP4307102A1
公开(公告)日：2024-01-17
申请号：EP22187804.4
申请日：2022-07-29
申请人： Siemens Aktiengesellschaft
发明人： De Santis, Fabrizio , Furch, Andreas , Safieh, Malek
IPC分类号： G06F7/48 , G06F7/72
摘要： Computer-implemented method for determining a Gaussian integer congruent to a given Gaussian integer modulo a Gaussian integer modulus, wherein the norm of the Gaussian integer is smaller than the norm of the square of the Gaussian integer modulus, wherein a real integer base raised to a first integer exponent having a norm larger than that of the real and larger than that of the imaginary part of the Gaussian integer modulus is considered, wherein a second integer exponent is considered that is equal to or smaller than -2 and wherein a third integer exponent is considered, that is equal to or larger than the first integer exponent raised by one, and wherein a variable value candidate for the Gaussian integer congruent is considered that is first initialized with the given Gaussian integer and wherein the Gaussian integer is, either fully or in truncated form, decremented by a multiple of the Gaussian integer modulus, wherein the multiple of the Gaussian integer modulus is evaluated by calculating an auxiliary product of a component-wisely down rounded quotient of the current value of the variable value candidate for the Gaussian integer congruent and the real integer base raised to the sum of the first integer exponent and the second integer exponent with a prefactor and by calculating a component-wisely down rounded quotient of this auxiliary product and the real integer base raised to the difference of the third integer exponent and the second integer exponent and multiplying this latter quotient with the Gaussian integer modulus.
In the Computer-implemented method for determining a reduction of a given Gaussian integer modulo a Gaussian integer modulus first a Gaussian integer congruent to a modulo reduction of a given Gaussian integer modulo a Gaussian integer modulus is determined with the method described before and the Gaussian integer congruent is further reduced with a final reduction.
These methods are used in computer-implemented cryptographic methods and error-correction methods.

5. 发明授权

EP3480998B1 OPERATION METHOD AND SECURITY CHIP 有权
公开(公告)号：EP3480998B1
公开(公告)日：2022-02-09
申请号：EP17833536.0
申请日：2017-07-25
发明人： HU, Cui , TAN, ZhuFeng , SUN, Shaojie
IPC分类号： H04L9/00 , G06F21/72 , G06F7/72

6. 发明公开

EP3885896A1 FLOAT DIVISION BY CONSTANT INTEGER WITH OUTPUT SUBTRACTION 有权
公开(公告)号：EP3885896A1
公开(公告)日：2021-09-29
申请号：EP21174954.4
申请日：2019-08-22
申请人： Imagination Technologies Limited
发明人： KÁLLÉN, Jonas , ELLIOTT, Sam
IPC分类号： G06F7/535 , G06F7/72
摘要： A binary logic circuit for determining the ratio x / d where x is a variable integer input of w bits comprising M > 8 blocks of bit width r ≥ 1 bit, and d > 2 is a fixed integer, the binary logic circuit comprising a logarithmic tree of modulo units each configured to calculate x [ a : b ] mod d for respective block positions a and b in x where b > a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M - 1 modulo units of the logarithmic tree provide x[0: m ] mod d for all m ∈ {1, M}, and, on the basis that any given modulo unit introduces a delay of 1, all of the modulo units are arranged in the logarithmic tree within a delay envelope of ┌ log 2 M ┐, and at least one of the subset of modulo units is arranged to operate on a binary value comprising the negative value of (a) an output from a modulo unit x[e: f]mod d or (b) input block(s) x [ e : f ] and the value of x [ 0: f ] mod d so as to calculate x [ 0: e ] mod d, where e and f are block positions in x,and output logic configured to combine the outputs provided by the subset of modulo units with blocks of the input x so as to yield the ratio x / d.

7. 发明授权

EP3614257B1 FLOAT DIVISION BY CONSTANT INTEGER 有权
公开(公告)号：EP3614257B1
公开(公告)日：2021-06-30
申请号：EP19193067.6
申请日：2019-08-22
发明人： KÄLLÉN, Jonas , ELLIOTT, Sam
IPC分类号： G06F7/535 , G06F7/72

8. 发明授权

EP3542262B1 PUNKTMULTIPLIKATION AUF EINER ERWEITERUNG EINER ELLIPTISCHEN KURVE 有权转让
公开(公告)号：EP3542262B1
公开(公告)日：2021-01-06
申请号：EP17800702.7
申请日：2017-11-15
发明人： SEYSEN, Martin
IPC分类号： G06F7/72 , H04L9/00 , H04L9/30

9. 发明公开

EP3716044A1 PROTECTION D'UN CALCUL ITÉRATIF 有权
公开(公告)号：EP3716044A1
公开(公告)日：2020-09-30
申请号：EP20166467.9
申请日：2020-03-27
申请人： STMicroelectronics (Rousset) SAS
发明人： DIOP, Ibrahima , LINGE, Yanis
IPC分类号： G06F7/72
摘要： La présente description concerne un procédé de protection d'un calcul sur un premier nombre (M) et un deuxième nombre (e), exécuté par un circuit électronique, dans lequel : le deuxième nombre (e) est décomposé en une somme d'au moins deux troisièmes nombres (X1, X2) ; et le calcul est effectué bit par bit pour chaque rang (i) des troisièmes nombres (X1, X2).

10. 发明授权

EP3087470B1 RSA ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
公开(公告)号：EP3087470B1
公开(公告)日：2020-03-25
申请号：EP13900536.7
申请日：2013-12-28
申请人： Intel Corporation
发明人： LU, Yang , SUN, Xiangzheng , QIAO, Nan Stan
IPC分类号： G06F7/544 , G06F7/72 , G06F9/30

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